Samsung S3C2501X User Manual page 39

PRODUCT OVERVIEW
Group Pin Name
Memory ADDR[23:0]
Interface ADDR[10]/AP
(80)
XDATA[31:0]
nSDCS[1:0]
nSDRAS
nSDCAS
CKE
nSDWE/nWE16
1-14
Table 1-1. S3C2501X Signal Descriptions (Continue)
Pin Type Pad Type
24 O
32 I/O
2 O
1 O
1 O
1 O
1 O
Phot20 Address bus.
The 24-bit address bus covers the full 16 M
word address range of each ROM/SRAM
/FLASH and external I/O bank.
In the SDRAM interface, ADDR[14:13] is
always used as bank address of SDRAM
devices. If SDRAM devices with 2 internal
bank is used, ADDR[13] should be connected
to the BA of SDRAM. If SDRAM devices with
4 internal bank is used, ADDR[14:13] should
be connected to the BA[1:0] of SDRAM.
ADDR[10]/AP is the auto precharge control
pin. The auto precharge command is issued at
the same time as burst read or burst write by
asserting high on ADDR[10]/AP.
phbsut20 External bi-directional 32bit data bus.
The S3C2501X supports 8 bit, 16bit, 32bit bus
with ROM/SRAM/Flash/Ext IO bank, but
supports 16 bit or 32 bit bus with SDRAM
bank.
phot20 Not chip select strobe for SDRAM.
Two SDRAM banks are supported.
phot20 Not row address strobe for SDRAM.
NSDRAS signal is used for both SDRAM
banks.
phot20 Not column address strobe for SDRAM.
NSDCAS signal is used for both SDRAM
banks.
phob12 Clock Enable for SDRAM
CKE is clock enable signal for SDRAM.
phot20 Not Write Enable for SDRAM or 16 bit
ROM/SRAM.
This signal is always used as write enable of
SDRAM and is used as write enable of only
16-bit ROM/SRAM/Flash.
(That is, It is not enabled for 8 bit Memory)
S3C2501X
Description