Bncon - Samsung S3C2501X User Manual

MEMORY CONTROLLER
5.6.3.1 Ext I/O Bank Access Control Registers (BnCON)
The Ext I/O Bank controller has eight external I/O access control registers. These registers correspond to up to
eight external I/O banks that are supported by S3C2501X. Table 5-16 describes eight registers that are used to
control the timing of external I/O bank accesses.
The external I/O access cycles can be controlled by using either a specified value or an external wait signal,
nEWAIT. Especially, to obtain access cycles that are longer than TACC of 31 cycles, you can delay the active
time of nOE or nWBE by nEWAIT assertion. In case of ROM bank, nOE/nWBE signals are activated
simultaneously; that is, there is no control parameter as like TCOS.
Address setup time(TACS) can be used when the external memory access is handled by the nOE assertion to be
delayed. Thus the external memory may use more stable address. Access cycles(TACC) extend nCS cycles to
access external memory. After nOE is deasserted, chip selection hold time(TCOH) can be used when nCS is
keep up.
B0CON is used to set the external access timings for external I/O bank 0. B1CON is used to set the external
access timing for I/O bank 1, and so on.
The Ext I/O Bank controller has eight kind control registers for ROM, SRAM, and flash memory (see Table 5-16).
These registers correspond to up to eight ROM/SRAM/Flash banks that are supported by S3C2501X.
For ROM/SRAM/Flash bank 0, the external data bus width is determined by the signal at the B0SIZE pins:
When B0SIZE[1:0] = "01", the external bus width for ROM/SRAM/Flash bank 0 is 8 bits.
When B0SIZE[1:0] = "10", the external bus width for ROM/SRAM/Flash bank 0 is 16 bits.
When B0SIZE[1:0] = "11", the external bus width for ROM/SRAM/Flash bank 0 is 32 bits.
BnCON register configuration is described in Figure 5-11.
5-22

BnCON

Bank number
Figure 5-10. BnCON
S3C2501X