Samsung S3C2501X User Manual page 41

PRODUCT OVERVIEW
Group Pin Name
Memory XBMREQ
Interface
(80)
XBMACK
TAP TCK
Control
(5)
TMS
TDI
TDO
nTRST
1-16
Table 1-1. S3C2501X Signal Descriptions (Continue)
Pin Type Pad Type
1 I
1 O
1 I
1 I
1 I
1 O
1 I
phicd External Master bus request.
An external bus master uses this pin to
request the external bus. When it activates the
XBMREQ, the S3C2501X drives the state of
external bus pins to high impedance. This lets
the external bus master take control of the
external bus. When it has control, the external
bus master assumes responsibity for SDRAM
refresh operation. The XBMREQ is
deactivated when the external bus master
releases the external bus. When this occurs,
the S3C2501X can get the control of the bus
and the XBMACK goes "low".
phob8 External bus Acknowledge.
phic JTAG Test Clock.
The JTAG test clock shifts state information
and test data into, and out of, the S3C2501X
during JTAG test operations.
phicu JTAG Test Mode Select.
This pin controls JTAG test operations in the
S3C2501X. This pin is internally connected
pull-up.
phicu JTAG Test Data In.
The TDI level is used to serially shift test data
and instructions into the S3C2501X during
JTAG test operations. This pin is internally
connected pull-up.
phot12 JTAG Test Data Out.
The TDO level is used to serially shift test
data and instructions out of the S3C2501X
during JTAG test operations.
phicu JTAG Not Reset.
Asynchronous reset of the JTAG logic.
This pin is internally connected pull-up.
S3C2501X
Description