Data Structure Of Tx Buffer Descriptor - Samsung S3C2501X User Manual

32-bit risc microprocessor
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ETHERNET CONTROLLER
31
30
O
TxStatus
[31:0]
Buffer pointer
[31]
Ownership bit (O) 0 = CPU
[30:18]
TxStatus
[30] Reserved
[29] Paused
[28] Halted
[27] SQEErr
[26] Defer
[25] Coll
[24] Comp
[23] ParErr
[22] LateColl
[21] NoCarr
[20] DeferErr
[19] Underflow
[18] ExColl
[17:16]
TxWidget
[15:0]
TxLength
7-10
18 17
16
15
Buffer Pointer
TxWidget
Address of the data be transmitted.
1 = BDMA
Writing in this field don't have any mean.
Transmission of frame was paused due to the reception of a Pause control frame.
The transmission of the next frame is halted when MACCON.1 (MHaltImm) is set,
or when MACTXCON.0 (MTxEn) is clear.
Signal Quality Error
The transmission of frame was deferred.
The collision is occured in half-duplex. The current frame is retried to send.
The transmition is finished.
MTxFIFO Parity Error
The Collision occured after 64 byte times.
No Carrier sense is detected when MAC Tx transmits a frame.
MAC doesn't run the transmission process until 6071-nibble or 24284-bit times.
The current frame is aborted.
MTxFIFO underflow
The excessive collision is occured 16 times consecutively.
The current frame is aborted.
The transmission widget alignment of the current frame.
The size of the transmission data by using the BDMA.
The Unit of the length field is the byte and the hexdecimal number.
Figure 7-2. Data Structure of Tx Buffer Descriptor
TxLength
S3C2501X
0

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