ETHERNET CONTROLLER
7.4.2.7 MAC Receive Status Register
A receive status flag is set in the MAC receive status register, MACRXSTAT, whenever the corresponding event
occurs. When a status flag is set, it remains set until another packet arrives, or until software writes a '1' to the
flag to clear the status bit. If the corresponding interrupt enable bit in the receive control register is set, an
interrupt is generated whenever a status flag is set. A MAC receive parity error sets RxParErr, and also clears
the MRxEn bit (if an interrupt is enabled).
Registers
Address
MACRXSTATA
0xF00B0014
MACRXSTATB
0xF00D0014
Bit Number
[7:0]
[8]
Short Frame Error (MRxShort) This bit is set if the frame was received with short frame.
[9]
Receive 10-Mb/s status
(MRx10Stat)
[10]
Reception halted (MRxHalted) This bit is set if the MRxEn bit is cleared or the MHaltImm bit
[11]
Control frame received
(MCtlRecd)
[31:12]
Reserved
7-30
Table 7-21. MACRXSTAT Register
R/W
R/W
R/W
Bit Name
–
These bits are equal to the BMRXSTAT.7-0
This bit is set to '1' if the frame was received over the 7-wire
interface or to '0' if the frame was received over the MII.
is set.
This bit is set if the frame received is a MAC control frame
(type = 0x8808), if the CAM recognizes the frame address,
and if the frame length is 64 bytes.
Not applicable.
Description
Receive status
Receive status
Description
S3C2501X
Reset Value
0x00000000
0x00000000