Samsung S3C2501X User Manual page 324

S3C2501X
7.4.2.12 MAC Received Pause Count Register
The received pause count register, PZCNT, stores the current value of the 16-bit received pause counter.
Registers Address
PZCNTA 0XF00B0040
PZCNTB 0XF00D0040
Bit Number
[15:0] Pause count received
7.4.2.13 MAC Remote Pause Count Register
Registers Address
RMPZCNTA 0xF00B0044
RMPZCNTB 0xF00D0044
Bit Number
[15:0] Remote pause count
Table 7-26. PZCNT Register
R/W
R
R
Bit Name
The count value indicates the number of time slots the
transmitter was paused due to the receipt of control pause
operation frames from the MAC.
Table 7-27. RMPZCNT Register
R/W
R
R
Bit Name
The count value indicates the number of time slots that a
remote MAC was paused as a result of its sending control
pause operation frames.
Description
Pause count
Pause count
Description
Description
Remote pause count
Remote pause count
Description
ETHERNET CONTROLLER
Reset Value
0x00000000
0x00000000
Reset Value
0x00000000
0x00000000
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