Samsung S3C2501X User Manual page 398

S3C2501X
Table 11-3 High-Speed UART Control Register Description (Continued)
Bit Number
[11] Number of Stop bits
(STB)
[13:12] Word Length (WL)
[14] Infra-red mode (IR)
[15] Reserved
[16] Transmit FIFO enable
(TFEN)
[17] Receive FIFO enable
(RFEN)
[18] Transmit FIFO reset
(TFRST)
[19] Receive FIFO reset
(RFRST)
[21:20] Transmit FIFO trigger
level (TFTL)
[23:22] Receive FIFO trigger
level (RFTL)
[24] Data Terminal Ready
to pin (DTR)
Bit Name
This bit specifies how many stop bits are used to signal end-of-frame
(EOF).
0 = one stop bit per frame
This two bit word length value indicates the number of data bits to be
transmitted or received per frame.
00 = 5-bit
The S3C2501X High-Speed UART block supports infra-red (IR)
transmits and receives operations. In IR mode, the transmit period is
pulsed at a rate of 3/16 that of the normal serial transmit rate (when
the transmit data value in the HUTXBUF register is zero).
To enable IR mode operation, you set HUCON[14] to "1". Otherwise,
the High-Speed UART operates in normal mode. In IR receive mode,
the receiver must detect the 3/16 pulsed period to recognize a zero
value in the receiver buffer register, HURXBUF, as the IR receive
data.
When this bit is "0", normal High-Speed UART mode is selected.
When it is "1", infra-red Tx/Rx mode is selected.
NOTE:
This bit should be cleared by zero.
S3C2501X High-Speed UART block support 32-byte FIFO. If this bit
set to one, transmit data moved to Tx FIFO and then sent.
S3C2501X High-Speed UART block support 32-byte FIFO. If this bit
set to one, receive data moved to Rx FIFO.
NOTE:
You set this bit to '1', transmit FIFO will be reset. In this case, if there
is data in transmit shift register, it will be sent.
NOTE:
You set this bit to '1', receive FIFO will be reset. In this case, if there is
data in receive shift register, it will be received.
NOTE:
This two bit trigger level value determines when the transmitter start to
transmit data in 32-byte transmit FIFO.
00 = 30-byte empty/32-byte
10 = 16/32
This two bit trigger level value determines when the receiver starts to
move the received data in 32-byte receive FIFO.
00 = 1-byte valid/32-byte
10 = 18/32
This bit directly controls the HUnDTR pin. Setting this bit to one, the
HUnDTR pin goes to Low level. If you set this bit to zero, it goes High
level.
Description
1 = two stop bit per frame
01 = 6-bit 10 = 7-bit
Changing this bit while tranmitting cause one Tx data losing.
Because level of infra-red frame start bit and idle state of
normal frame are identically high.
Changing these bits (TFEN, RFEN) while transmitting/receiving
sending/receiving unexpected data. To prevent this, changing
these bits while transmitting/receiving is strictly prohibited.
This bit will not cleared automatically.
This bit will not cleared automatically.
01 = 24/32
11 = 8/32
01 = 8/32
11 = 28/32
SERIAL I/O (HIGH-SPEED UART)
11 = 8-bit
11-5