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• Boot from serial TWI memory (EEPROM/flash) – The Blackfin
processor operates in master mode and selects the TWI slave with
the unique id 0xA0. It submits successive read commands to the
memory device starting at two byte internal address 0x0000 and
begins clocking data into the processor. The TWI memory device
should comply with Philips I
have the capability to auto-increment its internal address counter
such that the contents of the memory device can be read
sequentially.
• Boot from TWI host – The TWI host agent selects the slave with
the unique id 0x5F. The processor replies with an acknowledge-
ment and the host can then download the boot stream. The TWI
host agent should comply with Philips I
2.1. An I
time when booting multiple processors from a single TWI.
For each of the boot modes, a 10-byte header is first read from an external
memory device. The header specifies the number of bytes to be transferred
and the memory destination address. Multiple memory blocks may be
loaded by any boot sequence. Once all blocks are loaded, program execu-
tion commences from the start of L1 instruction SRAM.
In addition, bit 4 of the reset configuration register can be set by applica-
tion code to bypass the normal boot sequence during a software reset. For
this case, the processor jumps directly to the beginning of L1 instruction
memory.
Instruction Set Description
The ADSP-BF53x processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and readability.
Refer to the ADSP-BF53x/BF56x Blackfin Processor Programming Reference
for detailed information. The instructions have been specifically tuned to
provide a flexible, densely encoded instruction set that compiles to a very
ADSP-BF537 Blackfin Processor Hardware Reference
2
C multiplexer can be used to select one processor at a
2
C Bus Specification version 2.1 and
2
C Bus Specification version
Introduction
1-27
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