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DMEM_CONTROL Register
The data memory control register (
contains control bits for the L1 data memory.
Data Memory Control Register (DMEM_CONTROL)
0xFFE0 0004
PORT_PREF1 (DAG1 Port
Preference)
0 - DAG1 non-cacheable fetches
use port A
1 - DAG1 non-cacheable fetches
use port B
PORT_PREF0 (DAG0 Port
Preference)
0 - DAG0 non-cacheable fetches
use port A
1 - DAG0 non-cacheable fetches
use port B
DCBS (L1 Data Cache Bank Select)
Valid only when DMC[1:0] = 11. Determines
whether Address bit A[14] or A[23] is used to
select the L1 data cache bank.
0 - Address bit 14 is used to select Bank A or B
for cache access. If bit 14 of address is 1,
select L1 Data Memory Data Bank A; if bit 14
of address is 0, select L1 Data Memory Data
Bank B.
1 - Address bit 23 is used to select Bank A or B for
cache access. If bit 23 of address is 1, select
L1 Data Memory Data Bank A; if bit 23 of
address is 0, select L1 Data Memory Data
Bank B.
Figure 3-4. L1 Data Memory Control Register
ADSP-BF537 Blackfin Processor Hardware Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
15 14 13 12 11 10
9
8
0
0
0
1
0
0
0
0
), shown in
DMEM_CONTROL
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Memory
Figure
3-4,
Reset = 0x0000 1001
ENDCPLB (Data Cacheability
Protection Lookaside Buffer
Enable)
0 - CPLBs disabled. Minimal
address checking only
1 - CPLBs enabled
DMC[1:0] (L1 Data Memory
Configure)
For ADSP-BF534 and ADSP-BF537:
00 - Both data banks are
SRAM, also invalidates all
cache lines if previously
configured as cache
01 - Reserved
10 - Data Bank A is lower
16K byte SRAM, upper
16K byte cache
Data Bank B is SRAM
11 - Both data banks are
lower 16K byte SRAM,
upper 16K byte cache
For ADSP-BF536:
00 - Data Bank A is SRAM,
also invalidates all cache
lines if previously
configured as cache
01 - Reserved
10 - Data Bank A is cache
11 - Both data banks are
lower 16K byte SRAM,
upper 16K byte cache
3-9
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