Ddcmp Memory Map; Ddcmp Programming Model - Motorola MC68302 User Manual

clears the empty bit in the BD and generates a maskable received buffer
interrupt (RBD). If the incoming message exceeds the length of the data
buffer, the DDCMP controller fetches the next BD in the table, and, if it is
empty, continues to transfer the rest of the message to the new data buffer.
When the message ends, the CRC2 field is checked and written to the data
buffer. The DDCMP controller sets the last bit, writes the message type and
other status bits into the BD, and clears the empty bit. Following this, it
generates an RBK, indicating that a message has been received and is in
memory. The DDCMP controller then waits for a new message.
4.5.14.3 DDCMP MEMORY MAP.
When configured to operate in DDCMP mode,
the IMP overlays the structure illustrated in Table 4-6 onto the protocol-
specific area of that SCC's parameter RAM. Refer to 2.8 MC68302 MEMORY
MAP for the placement of the three SCC parameter RAM areas and to Table
4-2 for the other parameter RAM values.
Table 4-6. DDCMP-Specific Parameter RAM
Address Name Block Description
SCC Base+9C RCRC Word Temp Receive CRC
SCC Base+9E CRCC Word CRC16 Constant
SCC Base+AO
*
PCRC Word
Preset CRC16
SCC Base+A2 TCRC Word Temp Transmit CRC
SCC Base+A4
*
DSOH Word DDCMP SOH Character
SCC Base+A6
*
DENO Word
DDCMP ENO Character
SCC Base+A8
*
ODLE
Word DDCMP OLE Character
SCC Base+AA CRC1EC Word CRC1 Error Counter
SCC Base+ AC CRC2EC Word CRC2 Error Counter
SCC Base"- AE NM ARC Word Nonmatching Address Received Counter
SCC Base+ BO DISMC Word Discard Message Counter
SCC Base+ B2 RMLG Word Received Message Length
SCC Base+ B4 RMLG-CNT Word Received Message Length Counter
SCC Base+ B6
*
DMASK Word User Defined Frame Address Mask
SCC Base
t
B8
*
DADDR1 Word User Defined Frame Address
SCC Base+ BA
*
DADDR2
Word User Defined Frame Address
SCC Base+ BC
*
DADDR3 Word User Defined Frame Address
SCC Base+ BE
*
DADDR4 Word User Defined Frame Address
*Initialized by the user (M68000 core).
4.5.14.4 DDCMP PROGRAMMING MODEL. The M68000 core configures each SCC
to operate in one of four protocols by the MODE1-MODEO bits in the SCC
mode register. If MODE1-MODEO= 10, DDCMP operation is selected with
synchronous links. For asynchronous links, MODE1-MODEO= 01 (ASYNC)
MOTOROLA MC68302 USER'S
MANUAL
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