S1D13505 Host Bus Interface; Pr31500/Pr31700 Host Bus Interface Pin Mapping; Pr31500/Pr31700 Host Bus Interface Signals - Epson S1D13505F00A Technical Manual

4.3 S1D13505 Host Bus Interface

The S1D13505 implements a 16-bit host bus interface specifically for interfacing to the PR31500/
PR31700 microprocessor.
The PR31500/PR31700 host bus interface is selected by the S1D13505 on the rising edge of
RESET#. After releasing reset, the bus interface signals assume their selected configuration. For
details on S1D13505 configuration, see "S1D13505 Configuration" on page 14.
Note: At reset, the Host Interface Disable bit in the Miscellaneous Disable Register (REG[1Bh] bit 7) is set
to 1. This means that only REG[1Ah] (read-only) and REG[1Bh] are accessible until a write to
REG[1Bh] sets bit 7 to 0 making all registers accessible. When debugging a new hardware de-
sign, this can sometimes give the appearance that the interface is not working, so it is important to re-
member to clear this bit before proceeding with debugging.

PR31500/PR31700 Host Bus Interface Pin Mapping

The following table shows the function of each host bus interface signal.
Table 4-1 PR31500/PR31700 Host Bus Interface Pin Mapping
S1D13505 Pin Name
AB20
AB19
AB18
AB17
AB[16:13]
AB[12:0]
DB[15:8]
DB[7:0]
WE1#
M/R#
CS#
BUSCLK
BS#
RD/WR#
RD#
WE0#
WAIT#
RESET#

PR31500/PR31700 Host Bus Interface Signals

When the S1D13505 is configured to operate with the PR31500/PR31700, the host interface
requires the following signals:
• BUSCLK is a clock input required by the S1D13505 host bus interface. It is separate from the
input clock (CLKI) and should be driven by the PR31500/PR31700 bus clock output DCLKOUT.
• Address input AB20 corresponds to the PR31500/PR31700 signal ALE (address latch enable)
whose falling edge indicates that the most significant bits of the address are present on the multi-
plexed address bus (AB[12:0]).
• Address input AB19 should be connected to the PR31500/PR31700 signal /CARDREG. This sig-
nal is active when either IO or configuration space of the PR31500/PR31700
PC Card slot is being accessed.
• Address input AB18 should be connected to the PR31500/PR31700 signal /CARDIORD. Either
AB18 or the RD# input must be asserted for a read operation to take place.
APPLICATION NOTES (X23A-G-005-05)
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4: INTERFACING TO THE PHILIPS MIPS PR31500/PR31700 PROCESSOR
Philips PR31500/PR31700
ALE
/CARDREG
/CARDIORD
/CARDIOWR
V
DD
A[12:0]
D[23:16]
D[31:24]
/CARDxCSH
V
DD
V
DD
DCLKOUT
V
DD
/CARDxCSL
/RD
/WE
/CARDxWAIT
RESET#
EPSON
5-11