CC2652PSIP
SWRS263A – FEBRUARY 2021 – REVISED JUNE 2022
9 Detailed Description
9.1 Overview
Section 4
shows the core modules of the CC2652PSIP device.
9.2 System CPU
The CC2652PSIP SimpleLink
application and the higher layers of radio protocol stacks.
The system CPU is the foundation of a high-performance, low-cost platform that meets the system requirements
of minimal memory implementation, and low-power consumption, while delivering outstanding computational
performance and exceptional system response to interrupts.
Its features include the following:
•
ARMv7-M architecture optimized for small-footprint embedded applications
•
Arm Thumb
®
-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit Arm
core in a compact memory size
•
Fast code execution permits increased sleep mode time
•
Deterministic, high-performance interrupt handling for time-critical applications
•
Single-cycle multiply instruction and hardware divide
•
Hardware division and fast digital-signal-processing oriented multiply accumulate
•
Saturating arithmetic for signal processing
•
IEEE 754-compliant single-precision Floating Point Unit (FPU)
•
Memory Protection Unit (MPU) for safety-critical applications
•
Full debug with data matching for watchpoint generation
– Data Watchpoint and Trace Unit (DWT)
– JTAG Debug Access Port (DAP)
– Flash Patch and Breakpoint Unit (FPB)
•
Trace support reduces the number of pins required for debugging and tracing
– Instrumentation Trace Macrocell Unit (ITM)
– Trace Port Interface Unit (TPIU) with asynchronous serial wire output (SWO)
•
Optimized for single-cycle flash memory access
•
Tightly connected to 8-KB 4-way random replacement cache for minimal active power consumption and wait
states
•
Ultra-low-power consumption with integrated sleep modes
•
48 MHz operation
•
1.25 DMIPS per MHz
38
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™
Wireless MCU contains an Arm
Product Folder Links:
®
®
Cortex
-M4F system CPU, which runs the
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CC2652PSIP
www.ti.com
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