Multiple Interrupt Processing Control - NEC V850E/MS1 UPD703100 User Manual

7.6 Multiple Interrupt Processing Control

Multiple interrupt processing control is a process by which the interrupt request currently being processed can be
interrupted during processing if there is an interrupt request with a higher priority level, and the higher priority
interrupt request is acknowledged and processed first.
If there is an interrupt request with a lower priority level than the interrupt request currently being processed, that
interrupt request is held pending.
Maskable interrupt multiple processing control is executed when an interrupt has an enable status (ID = 0). Thus,
if multiple interrupts are executed, it is necessary to have an interrupt enable status (ID = 0) even for an interrupt
processing routine.
If a maskable interrupt or a software exception is generated in a maskable interrupt or software exception service
program, it is necessary to save EIPC and EIPSW.
This is accomplished by the following procedure.
(1) To acknowledge maskable interrupts in a service program
Service program of maskable interrupt or exception
...
...
• EIPC saved to memory or register
• EIPSW saved to memory or register
• EI instruction (enables interrupt acknowledgement)
...
...
...
...
• DI instruction (disables interrupt acknowledgement)
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
CHAPTER 7 INTERRUPT/EXCEPTION PROCESSING FUNCTION
User's Manual U12688EJ4V0UM00
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Maskable interrupt acknowledgement
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