Dual Quad-Spi Flash Memory - Xilinx KCU105 User Manual

Table 1-4: DDR4 Memory Connections to the FPGA (Cont'd)
FPGA Schematic Net
(U1) Pin
AL19 DDR4_CS_B
AD15 DDR4_CKE
AL18 DDR4_RESET_B
AE16 DDR4_CK_T
AE15 DDR4_CK_C
The KCU105 board DDR4 memory component interface adheres to the constraints
guidelines documented in the DDR4 Design Guidelines section of UltraScale Architecture
PCB Design User Guide (UG583)
Memory Interface Solutions LogiCORE IP Product Guide (PG150)
DDR4 memory component interface is a 40Ω impedance implementation. For more details
about the Micron DDR4 component memory, see the Micron EDY4016AABG-DR-F-D data
sheet at the Micron website

Dual Quad-SPI Flash Memory

[Figure 1-2, callout 3]
The Quad-SPI flash memory located at U35 and U36 provides 2 x 256 Mb of nonvolatile
storage that can be used for configuration and data storage. For details on FPGA
configuration operation and implementation related to the dual Quad-SPI interfaces, see
UltraScale Architecture Configuration User Guide (UG570)
• Part number: N25Q256A11ESF40F (Micron)
• Supply voltage: 1.8V
• Datapath width: 4 bits
• Data rate: various depending on single/dual/quad mode
KCU105 Board User Guide
UG917 (v1.4) September 25, 2015
I/O Standard
Name
SSTL12_DCI
SSTL12_DCI
LVCMOS12
DIFF_SSTL12_DCI
DIFF_SSTL12_DCI
[Ref 17]
[Ref 22].
www.xilinx.com
Chapter 1: KCU105 Evaluation Board Features
Component Memory
Pin #
L7
K2
P1
K7
K8
and in UltraScale Architecture-Based FPGAs
[Ref 3].
Pin Name Ref. Des.
CS_B U60-U62
CKE U60-U62
RESET_B U60-U62
CK_T U60-U62
CK_C U60-U62
[Ref 4]. The KCU105 board
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