Intel Agilex User Manual page 49

5. Intel Agilex High-Speed SERDES I/O Architecture
UG-20214 | 2019.04.02
Figure 35. Receiver Datapath in DPA Mode
This figure shows the DPA mode datapath. In the figure, all the receiver hardware blocks are active.
10 bits
maximum
data width
Note: In DPA mode, you must place all receiver channels of a SERDES instance in one I/O
sub-bank. Because each I/O sub-bank has a maximum of 12 1.5 V True Signaling I/O
buffer receiver pairs, each SERDES instance can support a maximum of 12 DPA
channels.
5.3.3.3. Soft-CDR Mode
The Intel Agilex SERDES channel offers the soft-CDR mode to support the GbE and
SGMII protocols. A receiver PLL uses the local clock source for reference.
Figure 36. Receiver Datapath in Soft-CDR Mode
This figure shows the soft-CDR mode datapath.
10 bits
maximum
data width
Send Feedback
IOE supports SDR, DDR, or non-registered datapath
2
10
rx_out
Deserializer
10
DOUT
FPGA
Fabric
(load_enable,
fast_clock)
rx_divfwdclk
rx_coreclock
DPA Clock Domain
SERDESClock Domain
IOE supports SDR, DDR, or non-registered datapath
2
10
rx_out
Deserializer
10
DOUT
FPGA
Fabric
(load_enable,
fast_clock)
rx_divfwdclk
rx_coreclock
DPA Clock Domain
SERDES Clock Domain
IOE
Bit Slip
Synchronizer
DIN DOUT DIN
DOUT
fast_clock
2
Clock Mux
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
I/O PLL
rx_inclock
Note: Disabled blocks and signals are grayed out
IOE
Bit Slip
Synchronizer
DIN DOUT DIN
DOUT
2 fast_clock
Clock Mux
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
I/O PLL
rx_inclock
Note: Disabled blocks and signals are grayed out
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
LVDS SERDES Receiver
+ rx_in
–
DPA Circuitry
Retimed
DIN Data DIN
DPA Clock
3
8 Serial DPA
Clock Phases
LVDS SERDES Receiver
+ rx_in
–
DPA Circuitry
Retimed
DIN Data DIN
DPA Clock
3
8 Serial DPA
Clock Phases
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