Intel Agilex User Manual page 14

General purpose i/o and lvds serdes
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I/O Standard
Current Strength
Table 5.
Intel Agilex Configuration Pin I/O Standards and Features
Configuration Pin
Function
TDO
TMS
TCK
TDI
nSTATUS
OSC_CLK_1
nCONFIG
SDM_IO[0],SDM_IO[8]
, SDM_IO[16]
SDM_IO[7:1],SDM_IO[
15:9]
AVST_CLK
AVST_READY
®
Intel
Agilex
General Purpose I/O and LVDS SERDES User Guide
14
Programmable IOE Feature
Slew Rate
Location
Direction
SDM I/O
Output
1.8 V LVCMOS
bank
SDM I/O
Input
Schmitt Trigger Input
bank
SDM I/O
Input
Schmitt Trigger Input
bank
SDM I/O
Input
Schmitt Trigger Input
bank
SDM I/O
Output
1.8V LVCMOS
bank
SDM I/O
Input
Schmitt Trigger Input
bank
SDM I/O
Input
Schmitt Trigger Input
bank
SDM I/O
I/O
Schmitt Trigger Input or
bank
1.8 V LVCMOS
SDM I/O
I/O
Schmitt Trigger Input or
bank
1.8 V LVCMOS
SDM
Input
1.2 V LVCMOS
Shared
GPIO bank
SDM
Output
1.2 V LVCMOS
Shared
GPIO bank
2. Intel Agilex I/O Features and Usage
Weak Pull-up/
Schmitt
Pull-down
Trigger/TTL
Input
Weak pull-
down with 20
kOhm resistor
Weak pull-
down with 50
kOhm resistor
Weak pull-
down with 80
kOhm resistor
I/O Standard
Drive
Strength
(mA)
8
8
8
Series 34
ohm on-
chip
termination
(OCT)
UG-20214 | 2019.04.02
Open Drain
Weak Pull-Up/Pull-
Down
Weak pull-up
Weak pull-up
Weak pull-down
Weak pull-up
Weak pull-up
Weak pull-down
Weak pull-up
Weak pull-down
Weak pull-up
continued...
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