Intel Agilex User Manual page 46

Figure 32. Receiver Data Realignment Rollover
This figure shows a preset value of four bit cycles before rollover occurs. The
for one
rx_coreclock
rx_inclock
rx_bitslip_ctrl
rx_coreclock
rx_bitslip_max
5.3.1.1.4. Deserializer
You can statically set the deserialization factor to x3, x4, x5, x6, x7, x8, x9, or x10 by
using the Intel Quartus Prime software.
The IOE contains two data input registers that can operate in DDR or SDR mode. You
can bypass the deserializer to support DDR (x2) and SDR (x1) operations.
Figure 33. Deserializer Bypass
This figure shows the deserializer bypass path.
rx_out
FPGA
Fabric
rx_divfwdclk
rx_coreclock
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
46
cycle to indicate that rollover has occurred.
IOE supports SDR, DDR, or non-registered datapath
2
IOE
2
Deserializer Bit Slip
10
DOUT DIN DOUT
2
(load_enable,
fast_clock) Clock Mux
3 (load_enable,
I/O PLL
5. Intel Agilex High-Speed SERDES I/O Architecture
Synchronizer
DIN
DOUT DIN
fast_clock
3
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
8 Serial fast_clock
fast_clock, rx_coreclock)
Clock Phases
Note: Disabled blocks and signals are grayed out
UG-20214 | 2019.04.02
signal pulses
rx_bitslip_max
LVDS SERDES Receiver
+ rx_in
–
DPA Circuitry
Retimed
Data DIN
DPA Clock
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