Intel Agilex User Manual page 36

• 12 pairs of dedicated SERDES transmitter channels.
• 12 pairs of dedicated SERDES receiver channels that support DPA and non-DPA
modes. Four pairs from the top sub-bank and eight pairs from the bottom sub-
bank dedicated SERDES receiver channels support Soft-CDR mode. Refer to the
Intel Agilex device pin-out files for the exact location of the Soft-CDR pins.
The SERDES transmitter and receiver channels are adjacent to each other. Refer to the
Intel Agilex device pin-out files for the exact location of the SERDES pins.
Figure 21. Intel Agilex I/O Subsystem (Bottom View)
HPS
HPS
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
36
Top I/O bank Row
3D 3C 3B
3A
2D 2C 2B 2A SDM
Bottom I/O bank Row
Top I/O bank Row
3D 3C 3B 3A
2D 2C 2B 2A
SDM
Bottom I/O bank Row
SDM Shared HPS Shared
GPIO Bank GPIO Bank
GPIO Bank SDM I/O Bank
HPS I/O Bank
Different device package has different I/O banks offering. Refer device pin-out files for available bank location for each device package.
5. Intel Agilex High-Speed SERDES I/O Architecture
I/O Center
OCT
I/O PLL
I/O Lane I/O Lane
Hard Memory
Controller
Hard Memory
Controller
I/O Lane I/O Lane
I/O PLL
OCT
I/O Center
I/O Center
OCT
I/O PLL
I/O VR
I/O Lane I/O Lane
Hard Memory
Controller
Hard Memory
Controller
I/O Lane I/O Lane
I/O PLL I/O VR
OCT
I/O Center
UG-20214 | 2019.04.02
I/O VR
I/O Lane I/O Lane
I/O Lane I/O Lane
I/O VR
I/O Lane
I/O Lane
I/O Lane I/O Lane
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