Intel Agilex User Manual page 28

Figure 15. POD12 I/O Standard External Termination
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
28
External
Termination in
Transmitter Pins
FPGA
Transmitter
OCT Termination
in Receiver Pins
Series
OCT in
OCT RS
Bidirectional
Pins
VCCIO
R
T
On-Board
On-Board
V
CCIO
Parallel
OCT, RT
50 Ω
VREF
VREF
FPGA
On-Board
3. Intel Agilex I/O Termination
UG-20214 | 2019.04.02
Receiver
V
CCIO
R
T
FPGA
V
CCIO
Series OCT RS
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