Intel Agilex User Manual page 37

5. Intel Agilex High-Speed SERDES I/O Architecture
UG-20214 | 2019.04.02
Figure 22. SERDES Circuitry
This figure shows a transmitter and receiver block diagram for the SERDES circuitry with the interface signals
of the transmitter and receiver data paths. The figure shows a transmitter and a receiver sharing an I/O PLL as
they are in the same sub-bank and using the same I/O PLL resource.In single data rate (SDR) and double data
rate (DDR) modes, the data widths are 1 and 2 bits, respectively.
10 bits
maximum
data width
Table 12. Supported Blocks and Modes for Data and Clock Path
Path
TX Data Path
RX Data Path
Send Feedback
Serializer
10
tx_in
DIN DOUT
tx_coreclock
(load_enable, fast_clock, tx_coreclock)
3
IOE supports SDR, DDR, or non-registered datapath
2
10
rx_out
Deserializer
10
DOUT DIN
FPGA
Fabric
(load_enable,
fast_clock)
rx_divfwdclk
rx_coreclock
DPA Clock Domain
SERDES Clock Domain
Mode
TX
DPA-FIFO
Soft-CDR
Intel
2
IOE
IOE supports SDR, DDR, or non-registered datapath
IOE
Bit Slip
Synchronizer
DOUT DIN
DOUT DIN
fast_clock
2
Clock Mux
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
Clock Phases
I/O PLL
rx_inclock / tx_inclock
Block
Serializer
DPA
Synchronizer
Bitslip
Deserializer
DPA
Bitslip
Deserializer
® ™
Agilex General Purpose I/O and LVDS SERDES User Guide
tx_out
+
–
LVDS SERDES Transmitter
LVDS SERDES Receiver
+ rx_in
–
DPA Circuitry
Retimed
Data DIN
DPA Clock
3
8 DPA
Clock Domain
SERDES clock domain
DPA clock domain
DPA-SERDES clock domain
crossing
SERDES clock domain
SERDES clock domain
DPA clock domain
DPA clock domain
DPA clock domain
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