Intel Agilex User Manual page 48

5.3.3.1. Non-DPA Mode
The non-DPA mode disables the DPA and synchronizer blocks. Input serial data is
registered at the rising edge of the serial
I/O PLLs.
The
fast_clock
and deserializer blocks.
Figure 34. Receiver Datapath in Non-DPA Mode
This figure shows the non-DPA datapath block diagram.
10 bits
maximum
data width
5.3.3.2. DPA Mode
The DPA block chooses the best possible clock (dpa_fast_clock) from the eight fast
clocks produced by the I/O PLL.
This serial
synchronizer. A serial
synchronizer. The same
deserializer blocks.
In DPA mode, the DPA FIFO synchronizes the re-timed data to the high-speed SERDES
clock domain. The DPA clock may shift phase during the initial lock period. To avoid
data run-through condition caused by the FIFO write pointer creeping up to the read
pointer, hold the FIFO in reset state until the DPA locks.
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
48
clock that is generated by the I/O PLLs clocks the data realignment
IOE supports SDR, DDR, or non-registered datapath
2
10
rx_out
Deserializer
10
DOUT
FPGA
Fabric
(load_enable,
fast_clock)
rx_divfwdclk
rx_coreclock
SERDES Clock Domain
clock is used for writing the serial data into the
dpa_fast_clock
fast_clock
fast_clock
5. Intel Agilex High-Speed SERDES I/O Architecture
clock that is produced by the
fast_clock
IOE
Bit Slip
Synchronizer
DIN DOUT DIN
DOUT
fast_clock
2
Clock Mux
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
I/O PLL
rx_inclock
Note: Disabled blocks and signals are grayed out
clock is used for reading the serial data from the
clock is used in data realignment and
UG-20214 | 2019.04.02
LVDS SERDES Receiver
+ rx_in
–
DPA Circuitry
Retimed
DIN Data DIN
DPA Clock
3
8 Serial DPA
Clock Phases
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