Intel Agilex User Manual page 6

In each sub-bank, there are four I/O lanes with 12 I/O pins in each lane that make up
a total of 48 single-ended I/O pins or 24 true differential I/O pairs per sub-bank. Each
I/O lane supports three differential receiver input buffer pairs with SERDES and
dynamic phase alignment (DPA) channels and three differential transmitter output
buffer pairs with SERDES channels.
Other than the I/O lanes, SERDES and DPA, each I/O sub-bank also contains
dedicated circuitries including I/O PLL, hard memory controller and OCT calibration
blocks.
The total bank count in a GPIO bank varies across different device packages. Certain
GPIO banks are shared with the SDM and HPS function blocks. Refer to the device pin-
out files for available GPIO banks, GPIO and SDM shared I/O banks, and GPIO and
HPS shared I/O banks per package.
The HPS I/O bank consists of 48 I/O pins. These pins are used for HPS clocks,
peripherals, mass storage flash and JTAG.
The SDM I/O bank consists of 24 dedicated pins for device configuration purposes.
Refer to the device pin-out files for the dedicated function of each pin in the SDM I/O
bank.
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Intel Agilex General Purpose I/O and LVDS SERDES User Guide
6
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1. Intel Agilex General Purpose I/O and LVDS SERDES Overview
UG-20214 | 2019.04.02
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