Pin Description; Datamemory; Special Function Registers - Intel MCS 51 User Manual

8XC52/54/58 HARDWARE DESCRIPTION
INTRODUCTION
The 8XC52/54/58 is a highly integrated 8-bit rnicro-
controlkx bed
onthe MCSQ-51architecture.The key
featuresare an enhanced serial pOrtfor multi-processor
communications and an up/down timer/counter. As
this product is CHMOS, it has two software selectable
reduced power modes: Idle Mode and Power Down
Mode. Being a member of the MCS-51 family, the
8XC52/54/58 is optimized for control applications.
This document presents a comprehensive descriptionof
the on-chip hardware features of the 8XC52/54/58 as
they ditTerfrom the 80C51BH. It begins by describing
how the 1/0 functions are different and then discusses
each of the peripheralsas follows:
256 Bytes on-chip RAM
Special Function Registers (SFR)
Timer 2
— CaptureTimer/Counter
— Up/Down Timer/Counter
— Baud Rate Generator
ble Serial Interface with
Full-Duplex Programma
— Framing Error Detection
— Automatic Address Recognition
6 InterruptSources
. Enhanced Power Down Mode
Power Off Flag
ONCE Mode
The 8XC52/54/58 uses the standard 8051 instruction
set and is pin-for-pin mmpatible with the existing
MCS-51 family of products. Table 1 summarks the
product names and memory differences of the various
8XC52/54/58 products currently available. Through-
out this documentj the products will generally be re-
ferred to as the 8XC5X.
Table1.8XC52/54/58Microcontrollers
~ ROM
I
EPROM I ROMlessl ROM/EPROM I RAM
1
Device Version Version
Bytes Bytes
80C52 87C52 80C32
8K 256
80C54 87C54 80C32
16K 256
80C58 87C56
80C32 32K 256
For a description of the features that are the same as
the 80C51, the reader should refer to the MCS-51 Ar-
chitectural Overview, MCS-51
Programmers G uide/
Instruction Set, and the Hardware Description of the
80C51 in the Embedded Microcontrollers ~d pr~
sors Handbook (Order #270645).
PIN DESCRIPTION
The
8XC5X pin-out is the same as the 80C51. The only
dit%rence is the rdternatefunction of pins P1.O and
P1.1. P1.Ois the external clock input for Timer 2. P1.1
is the Reload/Capture/Direction Control for Timer 2.
DATA MEMORY
The
8XC5X implements 256 bytes of on-chip RAM.
The upper 128 bytes occupy a parallel address space to
the Special Function Registers. That means they have
the same addresses, but they are physically separate
from SFR space.
When an instruction acceaaes an internal location above
address 7FH, the CPU knows whether the access is to
the upper 128 bytes of RAM or the SFR space by the
addressing mode used in the instruction. Instructions
that use direct addressingaccess SFR space. For exam-
ple,
MOV OAOH,#data (Direct Addressing)
accesses the SFR at location OAOH(which is P2). In-
structions that use indirect addressing access the upper
128 bytes of W. For example,
MOV @RO,#data (Indirect Addressing)
where ROcontains OAOH,accesses the data byte at ad-
dress OAOH,rather than P2 (whose address is OAOH).
Note that stack operations are examples of indirect ad-
dressing, so the upper 128 byteaof data RAM are avail-
able as stack space.
SPECIAL FUNCTION REGISTERS
A map of the on-chip memory area called the Special
Function Register (SFR) space is shown in Table 2.
Notethst not all ofthe addreaaes a re occupied, Unoc-
cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random dam and write amesses will have an indetermi-
nate effect.
User software should not write 1s to these unlisted lo-
cations, since they may be used in future MCS-51 prod-
ucts to invoke new features. In that case the reset or
inactive values of the new bits will always be O.
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