Intel Agilex User Manual page 7

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1. Intel Agilex General Purpose I/O and LVDS SERDES Overview
UG-20214 | 2019.04.02
Figure 2. Intel Agilex I/O Bank Structure (Bottom View)
This diagram shows the I/O bank structure of Intel Agilex AGF 012 and AGF 014 devices.
HPS
HPS
Send Feedback
Top I/O bank Row
3D 3C 3B
3A
2D 2C 2B 2A SDM
Bottom I/O bank Row
Top I/O bank Row
3D 3C 3B 3A
2D 2C 2B 2A
SDM
Bottom I/O bank Row
SDM Shared HPS Shared
GPIO Bank GPIO Bank
GPIO Bank SDM I/O Bank
HPS I/O Bank
Different device packages have a different number of I/O banks. Refer to the device pin-out files for available bank location for each device package.
I/O Center
OCT
I/O PLL I/O VR
I/O Lane I/O Lane
Hard Memory
Controller
Hard Memory
Controller
I/O Lane I/O Lane
I/O PLL
OCT
I/O Center
I/O Center
OCT
I/O PLL
I/O VR
I/O Lane I/O Lane
Hard Memory
Controller
Hard Memory
Controller
I/O Lane I/O Lane
I/O PLL I/O VR
OCT
I/O Center
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Intel Agilex General Purpose I/O and LVDS SERDES User Guide
I/O Lane
I/O Lane
I/O Lane I/O Lane
I/O VR
I/O Lane
I/O Lane
I/O Lane I/O Lane
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