Intel Agilex User Manual page 43

5. Intel Agilex High-Speed SERDES I/O Architecture
UG-20214 | 2019.04.02
RSDS, and LVPECL compatible signaling. You can statically set the I/O standard of the
receiver pins to 1.5 V True Differential Signaling in the Intel Quartus Prime software
Assignment Editor or
Note: The PLL that drives the SERDES channel must operate in integer PLL mode. You do not
need a PLL if you bypass the deserializer
Table 16. Dedicated Circuitry and Features of the LVDS SERDES Receiver
Dedicated Circuitry / Feature
Differential I/O buffer
SERDES
Phase-locked loops (PLLs)
Data realignment (Bit slip)
DPA
Synchronizer (FIFO buffer)
Skew adjustment
On-chip termination (OCT)
5.3.1.1. Receiver Blocks in Intel Agilex Devices
The Intel Agilex LVDS SERDES receiver has the following hardware blocks:
• DPA block
• Synchronizer
• Data realignment block (bit slip)
• Deserializer
Figure 29. Receiver Block Diagram
This figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is
1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and sends a
maximum of 10 bits to the internal logic.
10 bits
maximum
data width
Send Feedback
file.
.qsf
Supports 1.5V True Differential Signaling compatible with LVDS, RSDS, Mini-
LVDS, and LVPECL
Up to 10-bit wide deserializer
Generates different phases of a clock for data synchronizer
Inserts bit latencies into serial data
Chooses a phase closest to the phase of the serial data
Compensate for phase differences between the data and the receiver's input
reference clock
Manual
100 Ω in 1.5 V True Differential Signaling I/O standards
IOE supports SDR, DDR, or non-registered datapath
2
10
rx_out
Deserializer
10
DOUT
FPGA
Fabric
(load_enable,
fast_clock)
rx_divfwdclk
rx_coreclock
DPA Clock Domain
SERDES Clock Domain
Description
IOE
Bit Slip
Synchronizer
DIN DOUT DIN
DOUT
fast_clock
2
Clock Mux
(dpa_load_enable,
dpa_fast_clock, rx_divfwdclk)
3 (load_enable,
fast_clock, rx_coreclock)
I/O PLL
rx_inclock
® ™
Intel Agilex General Purpose I/O and LVDS SERDES User Guide
LVDS SERDES Receiver
+ rx_in
–
DPA Circuitry
Retimed
DIN Data DIN
DPA Clock
3
8 Serial DPA
Clock Phases
43