Intel Agilex User Manual page 44

5.3.1.1.1. DPA Block
The DPA block takes in high-speed serial data from the differential input buffer and
selects one of the eight phases that the I/O PLLs generate to sample the data. The
DPA chooses a phase closest to the phase of the serial data. The maximum phase
offset between the received data and the selected phase is 1/8 unit interval (UI)
which is the maximum quantization error of the DPA. The eight phases of the clock are
equally divided, offering a 45° resolution.
Figure 30. DPA Clock Phase to Serial Data Timing Relationship
This figure shows the possible phase relationships between the DPA clocks and the incoming serial data.
The DPA block continuously monitors the phase of the incoming serial data and selects
a new clock phase if required. You can prevent the DPA from selecting a new clock
phase by asserting the optional
channel.
DPA circuitry does not require a fixed training pattern to lock to the optimum phase
out of the eight phases. After reset or power up, the DPA circuitry requires transitions
on the received data to lock to the optimum phase. An optional output port,
rx_dpa_locked
phase after power up or reset. Use data checkers such as a cyclic redundancy check
(CRC) or diagonal interleaved parity (DIP-4) to validate the data.
An independent reset port,
must retrain the DPA circuitry after reset.
Note: The DPA block is bypassed in non-DPA mode.
(3)
The unit interval is the period of the clock running at the serial data rate (fast clock).
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Intel Agilex General Purpose I/O and LVDS SERDES User Guide
44
rx_in
D0 D1
0°
45°
90°
135°
180°
225°
270°
315°
0.125T vco
, is available to indicate an initial DPA lock condition to the optimum
rx_dpa_reset
5. Intel Agilex High-Speed SERDES I/O Architecture
D2 D3
T vco
T
VCO
port, which is available for each
rx_dpa_hold
, is available to reset the DPA circuitry. You
UG-20214 | 2019.04.02
D4 Dn
= PLL serial clock period
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(3)
,