Intel Agilex User Manual page 33

4. Intel Agilex I/O Design Guidelines
UG-20214 | 2019.04.02
• Example 1:
— When using 1.2 V LVCMOS, the output signal swings from 0 V to 1.2 V on a
lossless transmission line with no external pull-up or pull-down component.
You must ensure the
device is able to meet those conditions.
• Example 2:
— When using 1.2V voltage referenced I/O standards, the output signal swing
has a dependency on the external board termination or the receiver's internal
termination. The following diagram shows an example termination setup and
its equivalent circuit.
Figure 18. Termination Setup using 40 Ω RS OCT Driver with On-Board 50 Ω Pull-Up
Resistor to
When output buffer is driving HIGH, pin voltage is 0.93 V based on voltage divider
rule.
Figure 19. Equivalent Circuit of Example 2 with Output Buffer Driving HIGH
When output buffer is driving LOW, pin voltage is 0.27 V based on voltage divider rule.
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or
V
IH
/2
VCCIO_PIO
Rs OCT
40 Ω
FPGA
1.2 V
40 Ω
Intel
tolerance of the downstream connecting
V
IL
VCCIO/2
50 Ω
On-Board Receiver
Rs OCT Termination
0.6 V
50 Ω
Output buffer = HIGH
® ™
Agilex General Purpose I/O and LVDS SERDES User Guide
33