Intel Agilex User Manual page 45

5. Intel Agilex High-Speed SERDES I/O Architecture
UG-20214 | 2019.04.02
5.3.1.1.2. Synchronizer (DPA FIFO)
The synchronizer is a one-bit wide and six-bit deep FIFO buffer that compensates for
the phase difference between
fast_clock
phase differences, not frequency differences, between the data and the receiver's
input reference clock.
An optional port,
synchronizer. The synchronizer is automatically reset when the DPA first locks to the
incoming data. Use
indicates that the received data is corrupted.
Note: The synchronizer circuit is bypassed in non-DPA and soft-CDR mode.
5.3.1.1.3. Data Realignment Block (Bit Slip)
Skew in the transmitted data, along with skew added by the link, causes channel-to-
channel skew on the received serial data streams. If you enable the DPA, the received
data is captured with different clock phases on each channel. This difference may
cause misalignment of the received data from channel to channel. To compensate for
this channel-to-channel skew and establish the correct received word boundary at
each channel, each receiver channel has a dedicated data realignment circuit that
realigns the data by inserting bit latencies into the serial stream.
An optional
independently controlled from the internal logic. The data slips one bit on the rising
edge of
rx_bitslip_ctrl
include the following items:
• The minimum pulse width is one period of the parallel clock in the logic array.
• The minimum low time between pulses is one period of the parallel clock.
• The signal is an edge-triggered signal.
• The valid data is available four parallel clock cycles after the rising edge of
rx_bitslip_ctrl
The MSB from the serial data is not the MSB of the parallel data. You can use bit slip
to set the proper word boundary on the parallel data.
Figure 31. Data Realignment Timing
This figure shows receiver output (
The data realignment circuit has a bit slip rollover value set to the deserialization
factor. An optional status port,
each channel to indicate the reaching of the preset rollover point.
Send Feedback
dpa_fast_clock
that the I/O PLLs produce. The synchronizer can only compensate for
rx_fifo_reset
rx_fifo_reset
port controls the bit insertion of each receiver
rx_bitslip_ctrl
. The requirements for the
.
) after one bit slip pulse with the deserialization factor set to 4.
rx_out
rx_inclock
rx_in 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
rx_coreclock
rx_bitslip_ctrl
rx_out 3210
rx_bitslip_max
from the DPA block and the
, is available to the internal logic to reset the
to reset the synchronizer when the data checker
rx_bitslip_ctrl
321x 32x1 3x21
, is available to the FPGA fabric from
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Intel Agilex General Purpose I/O and LVDS SERDES User Guide
signal
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