Jtag Boundary-Scan Register; Boundary-Scan Cells In Intel Max 10 I/O Pin - Intel MAX 10 JTAG User Manual

2. JTAG BST Architecture
UG-M10JTAG | 2019.05.10
Figure 1. JTAG Circuitry Functional Model
• Test access port (TAP) controller—controls the JTAG BST.
• and
TMS
•
and
TDI
•
The
TDI
registers.
TDI
TMS
TCK

2.3. JTAG Boundary-Scan Register

You can use the boundary-scan register to test external pin connections or to capture
internal data. The boundary-scan register is a large serial shift register that uses the
pin as an input and the
TDI
of 3-bit peripheral elements that are associated with Intel MAX 10 I/O pins.

2.3.1. Boundary-Scan Cells in Intel MAX 10 I/O Pin

The Intel MAX 10 3-bit BSC contains the following registers:
•
Capture registers—connect to internal device data through
PIN_IN
•
Update registers—connect to external data through
Send Feedback
pins—operate the TAP controller.
TCK
pins—provide the serial path for the data registers.
TDO
pin also provides data to the instruction register to generate the control logic for the data
Instruction Register
UPDATEIR
CLOCKIR
SHIFTIR
TAP
Controller
Data Registers
UPDATEDR
CLOCKDR
SHIFTDR
pin as an output. The boundary-scan register consists
TDO
signals.
Instruction Decode
Bypass Register
Boundary-Scan Register
a
Device ID Register
ISP Registers
PIN_OUT
® ®
Intel MAX 10 JTAG Boundary-Scan Testing User Guide
TDO
, , and
OUTJ OEJ
and signals.
PIN_OE
5