Jumpers - Xilinx KCU116 User Manual

Jumpers

Figure 2-2 shows the KCU116 board jumper header locations. Each numbered component
shown in the figure is keyed to
references the respective schematic page numbers.
X-Ref Target - Figure 2-2
3
14
10 7
Table 2‐3: Default Jumper Settings
Jumper Function
J7 PCIe lane size select
J12 SYSMON_VP
J13 SYSMON_VN
J16 zSFP0 TX enable
J17 zSFP1 TX enable
J42 zSFP2 TX enable
J54 zSFP3 TX enable
J85 POR override
J90 SYSMON_VREFP select
J153 Maxim regulator inhibit
J165 System controller boot
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
Table 2-3, which identifies the default jumper settings and
2
12
5
8
6
9
4
Figure 2‐2: KCU116 Board Header Jumper Locations
Default
5-6 8-lane configuration
1-2 U1 VP pin P13 pull down 20.5K to GND
1-2 U1 VN pin R14 pull down 20.5K to GND
Off Disable zSFP0 TX, allow FPGA control
Off Disable zSFP1 TX, allow FPGA control
Off Disable zSFP2 TX, allow FPGA control
Off Disable zSFP3 TX, allow FPGA control
2-3 U1 POR_OVERRIDE pin Y12 to GND
1-2 SYSMON_VREFP = U64 1.25V VREF
Used only when programming power
Off
system
On = force Zynq-7000 AP SoC to boot in
Off
JTAG mode on power-up or reset
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Chapter 2: Board Setup and Configuration
11
Comments
1
13
X18420-120916
Figure 2‐2 Schematic
Callout Page
4 20
5 3
6 3
7 26
8 26
9 27
10 27
11 3
12 3
13 44
14 32
13
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