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Chapter 4: FPGA Configuration Options
Configuration Mode Jumper Settings (Header J30)
Select between three on-board configuration sources
4 Mbit Xilinx Platform Flash PROM
Configuration storage for Master Serial mode
The configuration mode jumpers determine which configuration mode the FPGA uses
when power is first applied, or whenever the PROG button is pressed.
The DONE pin LED lights when the FPGA successfully finishes configuration.
Pressing the PROG button forces the FPGA to restart its configuration process.
The 4 Mbit Xilinx Platform Flash PROM provides easy, JTAG-programmable configuration
storage for the FPGA. The FPGA configures from the Platform Flash using Master Serial
mode.
The 64-macrocell XC2C64A CoolRunner II CPLD provides additional programming
capabilities and flexibility when using the BPI Up, BPI Down, or MultiBoot configuration
modes and loading the FPGA from the StrataFlash parallel Flash PROM. The CPLD is user-
programmable.
Configuration Mode Jumpers
As shown in
mode. Inserting a jumper grounds the associated mode pin. Insert or remove individual
jumpers to select the FPGA's configuration mode and associated configuration memory
source.
26
DONE Pin LED
Lights up when FPGA successfully configured
Figure 4-2: Detailed Configuration Options
Table
4-1, the J30 jumper block settings control the FPGA's configuration
www.xilinx.com
PROG_B Push Button Switch
Press and release to restart configuration
64 Macrocell Xilinx XC2C64A CoolRunner CPLD
Controller upper address lines in BPI mode and
Platform Flash chip select (User programmable)
Spartan-3E Starter Kit Board User Guide
R
UG230_c4_02_030906
UG230 (v1.0) March 9, 2006
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