Jitter Attenuated Clock - Xilinx KC705 User Manual

Jitter Attenuated Clock

[Figure 1-2, callout 11]
The KC705 board includes a Silicon Labs Si5324 jitter attenuator U70 on the back side of the
board. FPGA user logic can implement a clock recovery circuit and then output this clock to
a differential I/O pair on I/O bank 13 (REC_CLOCK_C_P, FPGA U1 pin W27 and
REC_CLOCK_C_N, FPGA U1 pin W28) for jitter attenuation. The jitter attenuated clock
(SI5326_OUT_C_P, SI5326_OUT_C_N) is then routed as a reference clock to GTX Quad 116
inputs MGTREFCLK0P (FPGA U1 pin L8) and MGTREFCLK0N (FPGA U1 pin L7).
The Silicon Labs Si5324 U70 pin 1 reset net SI5326_RST must be driven High to enable the
device. U70 pin 1 net SI5326_RST is level-shifted to VADJ by U75 and is connected to U1
bank 12 pin AE20. An active-Low input performs an external hardware reset of the device.
This resets all internal logic to a known state and forces the device registers to their default
value. The clock outputs are disabled during reset. The part must be programmed after a
reset or power-up to get a clock output. The reset pin 1 has a weak internal pull-up.
The primary purpose of this clock is to support CPRI/OBSAI applications that perform clock
recovery from a user-supplied SFP/SFP+ module and use the jitter attenuated recovered
clock to drive the reference clock inputs of a GTX transceiver. The jitter attenuated clock
circuit is shown in
KC705 Evaluation Board
UG810 (v1.8) March 20, 2018
Figure 1-14.
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Chapter 1: KC705 Evaluation Board Features
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