Isb - ST STM32H7 Series Programming Manual

PM0214
3.11.5

ISB

Instruction synchronization barrier.
Syntax
ISB{cond}
Where: 'cond' is an optional condition code, see
Operation
ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so
that all instructions following the ISB are fetched from cache or memory again, after the ISB
instruction is completed.
Condition flags
This instruction does not change the flags.
Examples
ISB ; Instruction Synchronisation Barrier
The STM32 Cortex-M4 instruction set
Conditional execution on page
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