Pci Express* Based Interface Signals; Memory Channel Miscellaneous; Pci Express* Port 1 Signals; Pci Express* Port 2 Signals - Intel Xeon Processor E5-1600 Datasheet

Table 6-2.

Memory Channel Miscellaneous

DDR_RESET_C01_N
DDR_RESET_C23_N
DDR_SCL_C01
DDR_SCL_C23
DDR_SDA_C01
DDR_SDA_C23
DDR_VREFDQRX_C01
DDR_VREFDQRX_C23
DDR_VREFDQTX_C01
DDR_VREFDQTX_C23
DDR{01/23}_RCOMP[2:0]
DRAM_PWR_OK_C01
DRAM_PWR_OK_C23
6.2

PCI Express* Based Interface Signals

Note: PCI Express* Ports 1, 2 and 3 Signals are receive and transmit differential pairs.
Table 6-3.

PCI Express* Port 1 Signals

PE1A_RX_DN[3:0]
PE1A_RX_DP[3:0]
PE1B_RX_DN[7:4]
PE1B_RX_DP[7:4]
PE1A_TX_DN[3:0]
PE1A_TX_DP[3:0]
PE1B_TX_DN[7:4]
PE1B_TX_DP[7:4]
Table 6-4. PCI Express* Port 2 Signals (Sheet 1 of 2)
PE2A_RX_DN[3:0]
PE2A_RX_DP[3:0]
PE2B_RX_DN[7:4]
PE2B_RX_DP[7:4]
PE2C_RX_DN[11:8]
PE2C_RX_DP[11:8]
144
Signal Name
Signal Name
Signal Name
PCIe* Receive Data Input
PCIe* Receive Data Input
PCIe* Receive Data Input
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Description
System memory reset: Reset signal from processor to DRAM
devices on the DIMMs. DDR_RESET_C01_N is used for memory
channels 0 and 1 while DDR_RESET_C23_N is used for memory
channels 2 and 3.
SMBus clock for the dedicated interface to the serial presence
detect (SPD) and thermal sensors (TSoD) on the DIMMs.
DDR_SCL_C01 is used for memory channels 0 and 1 while
DDR_SCL_C23 is used for memory channels 2 and 3.
SMBus data for the dedicated interface to the serial presence
detect (SPD) and thermal sensors (TSoD) on the DIMMs.
DDR_SDA_C1 is used for memory channels 0 and 1 while
DDR_SDA_C23 is used for memory channels 2 and 3.
Voltage reference for system memory reads.
DDR_VREFDQRX_C01 is used for memory channels 0 and 1 while
DDR_VREFDQRX_C23 is used for memory channels 2 and 3.
Voltage reference for system memory writes.
DDR_VREFDQTX_C01 is used for memory channels 0 and 1 while
DDR_VREFDQTX_C23 is used for memory channels 2 and 3. These
signals are not connected.
System memory impedance compensation. Impedance
compensation must be terminated on the system board using a
precision resistor. See the appropriate Platform Design Guide
(PDG) for implementation details.
Power good input signal used to indicate that the VCCD power
supply is stable for memory channels 0 & 1 and channels 2 & 3.
Description
PCIe* Receive Data Input
PCIe* Receive Data Input
PCIe* Transmit Data Output
PCIe* Transmit Data Output
Description
Signal Descriptions
Datasheet Volume One