GE P4A Technical Manual page 23

P54A/B/C/E
Figure 79: Successful Autoreclose Signals logic diagram (Module 36)
Figure 80: Autoreclose Reset Successful Indication logic diagram (Module 37)
Figure 81: Circuit Breaker Healthy and System Check Timers Healthy logic diagram (Module 39)
Figure 82: Autoreclose Shot Counters logic diagram (Module 41)
Figure 83: CB Control logic diagram (Module 43)
Figure 84: Circuit Breaker Trip Time Monitoring logic diagram (Module 53)
Figure 85: AR Lockout Logic Diagram (Module 55)
Figure 86: Reset Circuit Breaker Lockout Logic Diagram (Module 57)
Figure 87: Pole Discrepancy Logic Diagram (Module 62)
Figure 88: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
Figure 89: Check Synchronisation Monitor for CB closure (Module 60)
Figure 90: Voltage Monitor for CB Closure (Module 59)
Figure 91: Three-phase Autoreclose System Check Logic Diagram (Module 45)
Figure 92: CB Manual Close System Check Logic Diagram (Module 51)
Figure 93: Circuit Breaker Fail logic - part 1
Figure 94: Circuit Breaker Fail logic - part 2
Figure 95: Circuit Breaker Fail logic - part 3
Figure 96: Circuit Breaker Fail logic - part 4
Figure 97: CB Fail timing
Figure 98: Phase Overcurrent Protection logic diagram
Figure 99: Negative Phase Sequence Overcurrent Protection logic diagram
Figure 100: IDG Characteristic
Figure 101: Earth Fault Protection logic diagram
Figure 102: EPATR B characteristic shown for TMS = 1.0
Figure 103: Sensitive Earth Fault Protection logic diagram
Figure 104: Current distribution in an insulated system with C phase fault
Figure 105: Phasor diagrams for insulated system with C phase fault
Figure 106: Positioning of core balance current transformers
Figure 107: High Impedance REF principle
Figure 108: High Impedance REF Connection
Figure 109: Thermal overload protection logic diagram
Figure 110: Spreadsheet calculation for dual time constant thermal characteristic
Figure 111: Dual time constant thermal characteristic
Figure 112: Broken conductor logic
Figure 113: Undervoltage - single and three phase tripping mode (single stage)
Figure 114: Overvoltage - single and three phase tripping mode (single stage)
Figure 115: Residual Overvoltage logic
Figure 116: Residual voltage for a solidly earthed system
Figure 117: Residual voltage for an impedance earthed system
Figure 118: Underfrequency logic (single stage)
P54xMED-TM-EN-1
Table of Figures
165
165
166
167
168
169
170
171
172
173
174
175
177
178
187
188
189
190
192
198
200
203
205
208
208
209
210
211
212
213
215
216
216
219
225
228
232
233
234
239
xxi