GE P4A Technical Manual page 21

Table of Figures
Figure 1: Key to logic diagrams
Figure 2: Functional Overview
Figure 3: Hardware architecture
Figure 4: Coprocessor hardware architecture
Figure 5: Exploded view of IED
Figure 6: Front panel (60TE)
Figure 7: Rear view of populated case
Figure 8: Terminal block types
Figure 9: Rear connection to terminal block
Figure 10: Main processor board
Figure 11: Power supply board
Figure 12: Power supply assembly
Figure 13: Power supply terminals
Figure 14: Watchdog contact terminals
Figure 15: Rear serial port terminals
Figure 16: Input module - 1 transformer board
Figure 17: Input module schematic
Figure 18: Transformer board
Figure 19: Input board
Figure 20: Standard output relay board - 8 contacts
Figure 21: IRIG-B board
Figure 22: Fibre optic board
Figure 23: Rear communication board
Figure 24: Ethernet board
Figure 25: Redundant Ethernet board
Figure 26: Fully populated Coprocessor board
Figure 27: Software Architecture
Figure 28: Frequency Response (indicative only)
Figure 29: Navigating the HMI
Figure 30: Default display navigation
Figure 31: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
Figure 32: Sample multi-ended system
Figure 33: Current differential discriminative criterion
Figure 34: Overall scheme designed for multi-ended differential protection
Figure 35: Two-ended transmission line
Figure 36: Ping-pong measurement for alignment of current signals
Figure 37: Snapshot of available data for processing at each terminal
Figure 38: CT saturation technique
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