GE P4A Technical Manual page 22

Table of Figures
Figure 39: Original current waveforms
Figure 40: Ipos and Ineg current waveforms
Figure 41: Internal external fault binary
Figure 42: CT Compensation
Figure 43: Permissive Intertripping example
Figure 44: Stub Bus protection
Figure 45: Six terminal, four junction topology and ring structure
Figure 46: Six terminal ring structure with channel allocation
Figure 47: Six terminal, four junction topology
Figure 48: Autoreclose sequence for a Transient Fault
Figure 49: Autoreclose sequence for an evolving or permanent fault
Figure 50: Autoreclose sequence for an evolving or permanent fault - single-phase operation
Figure 51: Key to logic diagrams
Figure 52: Autoreclose System Map - part 1
Figure 53: Autoreclose System Map - part 2
Figure 54: Autoreclose System Map - part 3
Figure 55: Autoreclose System Map - part 4
Figure 56: Autoreclose System Map - part 5
Figure 57: CB State Monitor logic diagram (Module 1)
Figure 58: Circuit Breaker Open logic diagram (Module 3)
Figure 59: CB In Service logic diagram (Module 4)
Figure 60: Autoreclose OK logic diagram (Module 8)
Figure 61: Autoreclose Enable logic diagram (Module 5)
Figure 62: Autoreclose Modes Enable logic diagram (Module 9)
Figure 63: Force Three-phase Trip logic diagram (Module 10)
Figure 64: Autoreclose Initiation logic diagram (Module 11)
Figure 65: Autoreclose Trip Test logic diagram (Module 12)
Figure 66: Autoreclose initiation by external trip or evolving conditions (Module 13)
Figure 67: Protection Reoperation and Evolving Fault logic diagram (Module 20)
Figure 68: Fault Memory logic diagram (Module 15)
Figure 69: Autoreclose In Progress logic diagram (Module 16)
Figure 70: Autoreclose Sequence Counter logic diagram (Module 18)
Figure 71: Single-phase Autoreclose Cycle Selection logic diagram (Module 19)
Figure 72: Three-phase Autoreclose Cycle Selection logic diagram (Module 21)
Figure 73: Dead time Start Enable logic diagram (Module 22)
Figure 74: Single-phase Dead Time logic diagram (Module 24)
Figure 75: Three-phase Dead Time logic diagram (Module 25)
Figure 76: Circuit Breaker Autoclose Logic Diagram (Module 32)
Figure 77: Prepare Reclaim Initiation Logic Diagram (Module 34)
Figure 78: Reclaim Time logic diagram (Module 35)
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P54A/B/C/E
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111
111
112
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115
115
116
130
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133
134
135
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148
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P54xMED-TM-EN-1