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GE P4A Technical Manual
Micom p40 agile single br eaker multi-end current differential ied (non distance)
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Contents
Table of Contents
Troubleshooting
Bookmarks
Table of Contents
Table of Contents
Chapter 1 Introduction
Circuit Breaker Fail Logic - Part
Rear Serial Port
Chapter Overview
Trip Circuit Supervision Scheme
Cip
Foreword
Target Audience
Typographical Conventions
Cip
Nomenclature
Compliance
Cip
Product Scope
Ordering Options
Cip
Features and Functions
Current Differential Protection Functions
Protection Functions
Control Functions
Measurement Functions
Communication Functions
Logic Diagrams
Figure 1: Key to Logic Diagrams
Functional Overview
Figure 2: Functional Overview
Chapter 2 Safety Information
Chapter Overview
Health and Safety
Symbols
Installation, Commissioning and Servicing
Lifting Hazards
Electrical Hazards
UL/CSA/CUL Requirements
Fusing Requirements
Equipment Connections
Protection Class 1 Equipment Requirements
Pre-Energisation Checklist
Peripheral Circuitry
Upgrading/Servicing
Decommissioning and Disposal
Regulatory Compliance
EMC Compliance: 2014/30/EU
LVD Compliance: 2014/35/EU
R&TTE Compliance: 2014/53/EU
UL/CUL Compliance
ATEX Compliance: 2014/34/EU
Chapter 3 Hardware Design
Chapter Overview
Hardware Architecture
Coprocessor Hardware Architecture
Figure 3: Hardware Architecture
Figure 4: Coprocessor Hardware Architecture
Mechanical Implementation
Housing Variants
Figure 5: Exploded View of IED
List of Boards
Front Panel
Front Panel Compartments
Figure 6: Front Panel (60TE)
Keypad
Front Serial Port (SK1)
Front Parallel Port (SK2)
Fixed Function Leds
Function Keys
Programable Leds
Rear Panel
Figure 7: Rear View of Populated Case
Figure 8: Terminal Block Types
Boards and Modules
Pcbs
Subassemblies
Figure 9: Rear Connection to Terminal Block
Main Processor Board
Figure 10: Main Processor Board
Power Supply Board
Figure 11: Power Supply Board
Figure 12: Power Supply Assembly
Watchdog
Figure 13: Power Supply Terminals
Rear Serial Port
Figure 14: Watchdog Contact Terminals
Input Module - 1 Transformer Board
Figure 15: Rear Serial Port Terminals
Figure 16: Input Module - 1 Transformer Board
Input Module Circuit Description
Figure 17: Input Module Schematic
Transformer Board
Figure 18: Transformer Board
Input Board
Figure 19: Input Board
Standard Output Relay Board
Figure 20: Standard Output Relay Board - 8 Contacts
IRIG-B Board
Figure 21: IRIG-B Board
Fibre Optic Board
Figure 22: Fibre Optic Board
Rear Communication Board
Ethernet Board
Figure 23: Rear Communication Board
Figure 24: Ethernet Board
Redundant Ethernet Board
Figure 25: Redundant Ethernet Board
Coprocessor Board
Current Differential Inputs
Coprocessor Board with 1PPS Input
Figure 26: Fully Populated Coprocessor Board
Chapter 4 Software Design
Chapter Overview
Sofware Design Overview
Figure 27: Software Architecture
System Level Software
Real Time Operating System
System Services Software
Self-Diagnostic Software
Startup Self-Testing
System Boot
System Level Software Initialisation
Platform Software Initialisation and Monitoring
Continuous Self-Testing
Platform Software
Record Logging
Settings Database
Interfaces
Protection and Control Functions
Acquisition of Samples
Frequency Tracking
Direct Use of Sample Values
System Level Software Initialisation
Fourier Signal Processing
Programmable Scheme Logic
Event Recording
Figure 28: Frequency Response (Indicative Only)
Disturbance Recorder
Fault Locator
Function Key Interface
Chapter 5 Configuration
Chapter Overview
Settings Application Software
Using the HMI Panel
Navigating the HMI Panel
Getting Started
Figure 29: Navigating the HMI
Default Display
Default Display Navigation
Figure 30: Default Display Navigation
Password Entry
Processing Alarms and Records
Menu Structure
Changing the Settings
Direct Access (the Hotkey Menu)
Setting Group Selection Using Hotkeys
Control Inputs
Circuit Breaker Control
Function Keys
Line Parameters
Tripping Mode
CB Trip Conversion Logic Diagram
Figure 31: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
Residual Compensation
Mutual Compensation
Date and Time Configuration
Using an SNTP Signal
Using an IRIG-B Signal
Using an IEEE 1588 PTP Signal
Without a Timing Source Signal
Time Zone Compensation
Daylight Saving Time Compensation
Settings Group Selection
Chapter 6 Current Differential Protection
Chapter Overview
Current Differential Protection Principle
Numerical Current Differential Protection
Multi-Ended Line Differential Protection
Basic Principles and Algorithm Design for Multi-Ended Differential Protection
Fault Discrimination
Differential Characteristics
Figure 32: Sample Multi-Ended System
Figure 33: Current Differential Discriminative Criterion
Basic Algorithm
Features of Multi-Ended Line Differential
Algorithm Overview
Communication Requirements
Figure 34: Overall Scheme Designed for Multi-Ended Differential Protection
Charging Current Compensation
Figure 35: Two-Ended Transmission Line
Synchronisation of Current Signals
Time Alignment Using Ping-Pong Technique
Figure 36: Ping-Pong Measurement for Alignment of Current Signals
Remote Terminal Time Alignment
Time Delay Interpolation
Figure 37: Snapshot of Available Data for Processing at each Terminal
CT Saturation
Figure 38: CT Saturation Technique
Figure 39: Original Current Waveforms
Figure 40: Ipos and Ineg Current Waveforms
Figure 41: Internal External Fault Binary
CT Compensation
Figure 42: CT Compensation
Current Differential Intertripping
Figure 43: Permissive Intertripping Example
Stub Bus Differential Protection
Figure 44: Stub Bus Protection
Application Notes
Multi-End Current Differential Protection
Figure 45: Six Terminal, Four Junction Topology and Ring Structure
Figure 46: Six Terminal Ring Structure with Channel Allocation
Feeder Topology
Configuring the Feeder Topology
Figure 47: Six Terminal, Four Junction Topology
Line Parameter Data
Configuring the Protection Communications
Setting up the Phase Differential Characteristic
Sensitivity under Heavy Loads
Permissive Intertripping
CT Ratio Correction Setting Guidelines
Feeders with Small Tapped Loads
Chapter 7 Autoreclose
Chapter Overview
Introduction to Autoreclose
Autoreclose Implementation
Autoreclose Logic Inputs from External Sources
Circuit Breaker Healthy Input
Inhibit Autoreclose Input
Block Autoreclose Input
Reset Lockout Input
Pole Discrepancy Input
External Trip Indication
Autoreclose Logic Inputs
Trip Initiation Signals
Circuit Breaker Status Inputs
System Check Signals
Autoreclose Logic Outputs
Autoreclose Operating Sequence
AR Timing Sequence - Transient Fault
AR Timing Sequence - Evolving/Permanent Fault
Figure 48: Autoreclose Sequence for a Transient Fault
AR Timing Sequence - Evolving/Permanent Fault Single-Phase
Figure 49: Autoreclose Sequence for an Evolving or Permanent Fault
Figure 50: Autoreclose Sequence for an Evolving or Permanent Fault - Single-Phase Operation
Autoreclose System Map
Figure 51: Key to Logic Diagrams
Autoreclose System Map Diagrams
Figure 52: Autoreclose System Map - Part 1
Figure 53: Autoreclose System Map - Part 2
Figure 54: Autoreclose System Map - Part 3
Figure 55: Autoreclose System Map - Part 4
Figure 56: Autoreclose System Map - Part 5
Autoreclose Internal Signals
Autoreclose DDB Signals
Logic Modules
Circuit Breaker Status Monitor
CB State Monitor Logic Diagram
Figure 57: CB State Monitor Logic Diagram (Module 1)
Circuit Breaker Open Logic
Circuit Breaker Open Logic Diagram
Circuit Breaker in Service Logic
Circuit Breaker in Service Logic Diagram
Figure 58: Circuit Breaker Open Logic Diagram (Module 3)
Figure 59: CB in Service Logic Diagram (Module 4)
Autoreclose OK Logic Diagram
Autoreclose Enable
Autoreclose Enable Logic Diagram
Autoreclose Modes
Figure 60: Autoreclose OK Logic Diagram (Module 8)
Figure 61: Autoreclose Enable Logic Diagram (Module 5)
Single-Phase and Three-Phase Autoreclose
Autoreclose Modes Enable Logic Diagram
AR Force Three-Phase Trip Logic
AR Force Three-Phase Trip Logic Diagram
Autoreclose Initiation Logic
Figure 62: Autoreclose Modes Enable Logic Diagram (Module 9)
Figure 63: Force Three-Phase Trip Logic Diagram (Module 10)
Autoreclose Initiation Logic Diagram
Autoreclose Trip Test Logic Diagram
Figure 64: Autoreclose Initiation Logic Diagram (Module 11)
Figure 65: Autoreclose Trip Test Logic Diagram (Module 12)
AR External Trip Initiation Logic Diagram
Figure 66: Autoreclose Initiation by External Trip or Evolving Conditions (Module 13)
Protection Reoperation and Evolving Fault Logic Diagram
Fault Memory Logic Diagram
Autoreclose in Progress
Figure 67: Protection Reoperation and Evolving Fault Logic Diagram (Module 20)
Figure 68: Fault Memory Logic Diagram (Module 15)
Autoreclose in Progress Logic Diagram
Sequence Counter
Figure 69: Autoreclose in Progress Logic Diagram (Module 16)
Autoreclose Sequence Counter Logic Diagram
Autoreclose Cycle Selection
Single-Phase Autoreclose Cycle Selection Logic Diagram
Figure 70: Autoreclose Sequence Counter Logic Diagram (Module 18)
Figure 71: Single-Phase Autoreclose Cycle Selection Logic Diagram (Module 19)
3-Phase Autoreclose Cycle Selection
Dead Time Control
Figure 72: Three-Phase Autoreclose Cycle Selection Logic Diagram (Module 21)
Dead Time Start Enable Logic Diagram
Figure 73: Dead Time Start Enable Logic Diagram (Module 22)
1-Phase Dead Time Logic Diagram
Figure 74: Single-Phase Dead Time Logic Diagram (Module 24)
3-Phase Dead Time Logic Diagram
Circuit Breaker Autoclose
Figure 75: Three-Phase Dead Time Logic Diagram (Module 25)
Circuit Breaker Autoclose Logic Diagram
Reclaim Time
Figure 76: Circuit Breaker Autoclose Logic Diagram (Module 32)
Prepare Reclaim Initiation Logic Diagram
Reclaim Time Logic Diagram
Figure 77: Prepare Reclaim Initiation Logic Diagram (Module 34)
Figure 78: Reclaim Time Logic Diagram (Module 35)
Succesful Autoreclose Signals Logic Diagram
Autoreclose Reset Successful Indication Logic Diagram
CB Healthy and System Check Timers
Figure 79: Successful Autoreclose Signals Logic Diagram (Module 36)
Figure 80: Autoreclose Reset Successful Indication Logic Diagram (Module 37)
CB Healthy and System Check Timers Logic Diagram
Autoreclose Shot Counters
Figure 81: Circuit Breaker Healthy and System Check Timers Healthy Logic Diagram (Module 39)
Autoreclose Shot Counters Logic Diagram
Figure 82: Autoreclose Shot Counters Logic Diagram (Module 41)
Circuit Breaker Control
CB Control Logic Diagram
Figure 83: CB Control Logic Diagram (Module 43)
Circuit Breaker Trip Time Monitoring
CB Trip Time Monitoring Logic Diagram
Autoreclose Lockout
Figure 84: Circuit Breaker Trip Time Monitoring Logic Diagram (Module 53)
CB Lockout Logic Diagram
Figure 85: AR Lockout Logic Diagram (Module 55)
Reset Circuit Breaker Lockout
Reset CB Lockout Logic Diagram
Figure 86: Reset Circuit Breaker Lockout Logic Diagram (Module 57)
Pole Discrepancy
Pole Discrepancy Logic Diagram
Circuit Breaker Trip Conversion
Figure 87: Pole Discrepancy Logic Diagram (Module 62)
CB Trip Conversion Logic Diagram
Monitor Checks for CB Closure
Figure 88: Circuit Breaker Trip Conversion Logic Diagram (Module 63)
Check Synchronisation Monitor for CB Closure
Figure 89: Check Synchronisation Monitor for CB Closure (Module 60)
Voltage Monitor for CB Closure
Synchronisation Checks for CB Closure
Figure 90: Voltage Monitor for CB Closure (Module 59)
Three-Phase Autoreclose System Check Logic Diagram
Figure 91: Three-Phase Autoreclose System Check Logic Diagram (Module 45)
CB Manual Close System Check Logic Diagram
Figure 92: CB Manual Close System Check Logic Diagram (Module 51)
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GE Energy Connections
Grid Solutions
MiCOM P40 Agile
P54A, P54B, P54C, P54E
Technical Manual
Single Breaker Multi-End Current Differential IED (Non Distance)
Hardware Version: M,P
Software Version: 01
Publication Reference: P54xMED-TM-EN-1
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Troubleshooting
Chapter 21 Maintenance and Troubleshooting
513
Troubleshooting
524
IEEE C37.94 fail
528
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