P54A/B/C/E
5.23.1
THREE-PHASE AUTORECLOSE SYSTEM CHECK LOGIC DIAGRAM
CB SC ClsNoDly
Enabled
CB SC CS1
Enabled
Check Sync 1 OK
CB SC CS2
Enabled
Check Sync 2 OK
CB SC DLLB
Enabled
Dead Line
Live Bus
CB SC LLDB
Enabled
Live Line
Dead Bus
CB SC DLDB
Enabled
Dead Line
Dead Bus
CB SC Shot 1
Disabled
Seq Counter = 1
CB SC all
Disabled
Ext CS OK
V03372
Figure 91: Three-phase Autoreclose System Check Logic Diagram (Module 45)
P54xMED-TM-EN-1
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Note: If the DDB signal Ext CS OK is not mapped in PSL , it defaults to High .
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Chapter 7 - Autoreclose
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CB Fast SCOK
1
1
CB SCOK
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