Using Size In The Index Selection - Motorola CPU32 Reference Manual

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D1
DLW
USED IN ADDRESS CALCULATION
Figure 3-3 Using SIZE in the Index Selection
For the CPU32, the register indirect modes can be extended further. Because dis-
placements can be 32 bits wide, they can represent absolute addresses or the results
of expressions that contain absolute addresses. This scheme allows the general reg-
ister indirect form to be (bd, Rn) or (bd, An, Rn) when the base register is not sup-
pressed. Thus, an absolute address can be directly indexed by one or two registers
(refer to Figure 3-4).
Setting the index register suppress bit (IS) in the full format extension word suppresses
the index operand. The indirect suppressed index register mode uses the contents of
register An as an index to the pointer located at the address specified by the displace-
ment. The actual data item is at the address in the selected pointer.
An optional scaling function supports direct array subscripting. An index register can
be left shifted by zero, one, two, or three bits before use in an EA calculation, to scale
for an array of elements of corresponding size. This is much more efficient than using
an arithmetic value in one of the general-purpose registers to multiply the index regis-
ter by one, two, four, or eight.
SYNTAX: (bd,An,Rn)
bd
An
Rn
Figure 3-4 Using Absolute Address with Indexes
Scaling does not add to the EA calculation time. However, when combined with the
appropriate derived modes, scaling produces additional capabilities. Arrayed struc-
tures can be addressed absolutely and then subscripted; for example, (bd, Rn ∗
SCALE). Optionally, an address register that contains a dynamic displacement can be
MOTOROLA DATA ORGANIZATION AND ADDRESSING CAPABILITIES CPU32
3-12 REFERENCE MANUAL