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8.1.5 Effects of Wait States
The CPU32 access time for on-chip memory and peripherals is two clocks. While two-
clock external accesses are possible when the bus is operated in a synchronous
mode, a typical external memory speed is three or more clocks.
All instruction times listed in this section are for word access only (unless an explicit
exception is given), and are based on the assumption that both instruction fetches and
operand cycles are to a two-clock memory. Any time a long access is made, time for
the additional bus cycle(s) must be added to the overall execution time. Wait states
due to slow external memory must be added to the access time for each bus cycle.
A typical application has a mixture of bus speeds —program execution from an off-chip
ROM, accesses to on-chip peripherals, storage of variables in slow off-chip RAM, and
accesses to external peripherals with speeds ranging from moderate to very slow. To
arrive at an accurate instruction time calculation, each bus access must be individually
considered. Many instructions have a head cycle count, which can overlap the cycles
of an operand fetch to slower memory started by a previous instruction. In these cases,
an increase in access time has no effect on the total execution time of the pair of in-
structions.
To trace instruction execution time by monitoring the external bus, note that the order
of operand accesses for a particular instruction sequence is always the same — pro-
vided bus speed is unchanged, the interleaving of instruction prefetches with operands
within each sequence is identical.
8.1.6 Instruction Execution Time Calculation
The overall execution time for an instruction depends on the amount of overlap with
previous and following instructions. In order to calculate an instruction time estimate,
the entire code sequence must be analyzed. To derive the actual instruction execution
times for an instruction sequence, the instruction times listed in the tables must be ad-
justed to account for overlap.
The formula for this calculation is:
− min (T
C
1
where:
C
is the number of cycles listed for instruction N
N
H
is the head time for instruction N
N
T
is the tail time for instruction N
N
min (T
, H
) is the minimum of parameters T
N
M
CPU32
REFERENCE MANUAL
) + C
− min (T
, H
1
2
2
INSTRUCTION EXECUTION TIMING
) + C
− min (T
, H
2
3
3
and H
N
M
) + ....
, H
3
4
MOTOROLA
8-5
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