Motorola CPU32 Reference Manual page 205

TBLS
TBLSN
Data Register Interpolate:
15 14 13
1 1 1
0 REGISTER Dx
Instruction Fields:
Effective address field (table lookup and interpolate mode only:
Specifies the source location. Only control addressing modes are allowed as
shown:
Addressing Mode
Dn
An
(An)
(An) +
– (An)
(d , An)
16
(d , An, Xn)
8
(bd, An, Xn)
Size field:
Specifies the size of operation.
Register field:
Specifies the destination data register, Dx. On entry, the register contains the
interpolation fraction and entry number.
Dym, Dyn field:
If the effective address mode field is nonzero, this operand register is unused
and should be zero. If the effective address mode field is zero, the surface
interpolation variant of this instruction is implied, and Dyn specifies one of the
two source operands.
Rounding mode field:
The 'R' bit controls rounding of the final result. When R = 0, the result is
rounded according to the round-to-nearest algorithm. When R = 1, the result is
returned unrounded.
CPU32
REFERENCE MANUAL
Table Lookup and Interpolate (Signed)
12 11 10 9
1 1 0 0
1 R 0
Mode Register
— —
— —
010 Reg. number: An
— —
— —
101 Reg. number: An
110 Reg. number: An
110 Reg. number: An
00 — byte operation
01 — word operation
10 — long operation
INSTRUCTION SET
8 7 6 5
0 0 0 0
0 SIZE 0
Addressing Mode
(xxx).W
(xxx).L
#〈data〉
(d , PC)
16
(d , PC, Xn)
8
(bd, PC, Xn)
TBLS
TBLSN
4 3 2 1
0 0 REGISTER Dym
0 0 REGISTER Dyn
Mode Register
111 000
111 001
— —
111 010
111 011
111 011
MOTOROLA
0
4-157