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8.3.2 Calculate Effective Address
The calculate effective address table indicates the number of clock periods needed for
the processor to calculate a specified effective address. The timing is equivalent to
fetch effective address except there is no read cycle. The tail and cycle time are re-
duced by the amount of time the read would occupy. The total number of clock cycles
is outside the parentheses. The numbers inside parentheses (r/p/w) are included in the
total clock cycle number. All timing data assumes two-clock reads and writes.
Dn
An
(An)
(An)+
−(An)
(d
,An) or (d
,PC)
16
16
(xxx).W
(xxx).L
(d
,An,Xn.Sz∗Sc) or (d
8
(0) (All Suppressed)
(d
)
16
(d
)
32
(An)
(Xm.Sz∗Sc)
(An,Xm.Sz∗Sc)
(d
,An) or (d
,PC)
16
16
(d
,An) or (d
,PC)
32
32
(d
,An,Xm) or (d
16
16
(d
,An,Xm) or (d
32
32
(d
,An,Xm.Sz∗Sc) or (d
16
(d
,An,Xm.Sz∗Sc) or (d
32
X = There is one bus cycle for byte and word operands and two bus cycles for long operands.
For long bus cycles, add two clocks to the tail and to the number of cycles.
NOTES:
1. Replacement fetches overlap the head of the operation by the amount specified in the tail.
2. Size and scale of the index register do not affect execution time.
3. The program counter may be substituted for the base address register An.
4. When adjusting the prefetch time for slower buses, extra clocks may be subtracted from
the head until the head reaches zero, at which time additional clocks must be added to
both the tail and cycle counts.
CPU32
REFERENCE MANUAL
Instruction
,PC,Xn.Sz∗Sc)
8
,PC,Xm)
,PC,Xm)
,PC,Xm.Sz∗Sc)
16
,PC,Xm.Sz∗Sc)
32
INSTRUCTION EXECUTION TIMING
Head
Tail
Cycles
–
–
0(0/0/0)
–
–
0(0/0/0)
1
0
2(0/0/0)
1
0
2(0/0/0)
2
0
2(0/0/0)
1
1
3(0/1/0)
1
1
3(0/1/0)
1
3
5(0/2/0)
4
0
6(0/1/0)
2
0
4(0/1/0)
1
1
5(0/2/0)
1
3
7(0/3/0)
1
0
4(0/1/0)
4
0
6(0/1/0)
4
0
6(0/1/0)
1
1
5(0/2/0)
1
3
7(0/3/0)
2
0
6(0/2/0)
1
1
7(0/3/0)
2
0
6(0/2/0)
1
1
7(0/3/0)
Notes
–
–
–
–
–
1,3
1
1
2,3,4
4
1,4
1,4
4
2,4
2,4
1,3,4
1,3,4
3,4
1,3,4
2,3,4
1,2,3,4
MOTOROLA
8-13
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