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The number of cycles for the instruction (C
address calculations in addition to the raw number in the cycles column. In these cas-
es, calculate overall instruction time as if it were for multiple instructions, using the fol-
lowing equation:
where:
〈CEA〉 is the instruction's effective address time
C
is the instruction's operation time
OP
H
is the instruction operation's head time
OP
T
is the effective address's tail time
EA
min (T
, H
) is the minimum of parameters T
N
M
The overall head for the instruction is the head for the effective address, and the over-
all tail for the instruction is the tail for the operation. Therefore, the actual equation for
execution time becomes:
C
OP1
Every instruction must prefetch to replace itself in the instruction pipe. Usually, these
prefetches occur during or after an instruction. A prefetch is permitted to begin in the
first clock of any indexed effective addressing mode operation.
Additionally, a prefetch for an instruction is permitted to begin two clocks before the
end of an instruction, provided the bus is not being used. If the bus is being used, then
the prefetch occurs at the next available time, when the bus would otherwise be idle.
8.1.7 Effects of Negative Tails
When the CPU32 changes instruction flow, the instruction decode pipeline must begin
refilling before instruction execution can resume. Refilling forces a two-clock idle peri-
od at the end of the change of flow instruction. This idle period can be used to prefetch
an additional word on the new instruction path.
Because of the stipulation that each instruction must prefetch to replace itself, the con-
cept of negative tails has been introduced to account for these free clocks on the bus.
On a two-clock bus, it is not necessary to adjust instruction timing to account for the
potential extra prefetch. The cycle times of the microsequencer and bus are matched
and no additional benefit or penalty is obtained. In the instruction execution time equa-
tions, a zero should be used instead of a negative number.
Negative tails are used to adjust for slower fetches on slower buses. Normally, in-
creasing the length of prefetch bus cycles directly affects the cycle count and tail val-
ues found in the tables.
MOTOROLA
8-6
〈CEA〉 − min (T
− min (T
) + 〈CEA〉
, H
OP1
EA2
− min (T
C
OP2
INSTRUCTION EXECUTION TIMING
above), can include one or two effective
N
) + C
, H
EA
OP
OP
and H
N
M
− min (T
2
EA2
) + ...
, H
OP2
EA3
) +
, H
OP2
CPU32
REFERENCE MANUAL
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