Processing Of Specific Exceptions - Motorola CPU32 Reference Manual

As a general rule, when simultaneous exceptions occur, the handler routines for lower
priority exceptions are executed before the handler routines for higher priority excep-
tions. For example, consider the arrival of an interrupt during execution of a TRAP in-
struction, while tracing is enabled. Trap exception processing (2) is done first, followed
immediately by exception processing for the trace (4.1), and then by exception pro-
cessing for the interrupt (4.3). Each exception places a new context on the stack.
When the processor resumes normal instruction execution, it is vectored to the inter-
rupt handler, which returns to the trace handler that returns to the trap handler.
There are special cases to which the general rule does not apply. The reset exception
will always be the first exception handled, since reset clears all other exceptions. It is
also possible for high priority exception processing to begin before low priority excep-
tion processing is complete. For example, if a bus error occurs during trace exception
processing, the bus error will be processed and handled before trace exception pro-
cessing is completed.

6.2 Processing of Specific Exceptions

The following paragraphs provide details concerning sources of specific exceptions,
how each arises, and how each is processed.
6.2.1 Reset
Assertion of RESET by external hardware, or assertion of the internal RESET signal
by an internal module, causes a reset exception. The reset exception has the highest
priority of any exception. Reset is used for system initialization and for recovery from
catastrophic failure. The reset exception aborts any processing in progress when it is
recognized, and that processing cannot be recovered. Reset performs the following
operations:
1. Clears T0 and T1 in the status register to disable tracing
2. Sets the S bit in the status register to establish supervisor privilege
3. Sets the interrupt priority mask to the highest priority level (%111)
4. Initializes the vector base register to zero ($00000000)
5. Generates a vector number to reference the reset exception vector
6. Loads the first long word of the vector into the interrupt stack pointer
7. Loads the second long word of the vector into the program counter
8. Fetches and initiates decode of the first instruction to be executed
Figure 6-2 is a flowchart of the reset exception.
After initial instruction prefetches, normal program execution begins at the address in
the program counter. The reset exception does not save the value of either the pro-
gram counter or the status register.
If a bus error or address error occurs during reset exception processing sequence, a
double bus fault occurs. The processor halts, and the HALT signal is asserted to indi-
cate the halted condition.
Execution of the RESET instruction does not cause a reset exception nor does it affect
any internal CPU register, but it does cause the CPU32 to assert the RESET signal,
resetting all internal and external peripherals.
CPU32
REFERENCE MANUAL
EXCEPTION PROCESSING MOTOROLA
6-5