Command Set - Motorola CPU32 Reference Manual

Figure 7-9 represents a sample circuit providing for both BKPT assertion methods. As
the name implies, FORCE_BGND is used to force a transition into BDM by the asser-
tion of BKPT. FORCE_BGND can be a short pulse or can remain asserted until
FREEZE is asserted. Once asserted, the set-reset latch holds BKPT low until the first
SHIFT_CLK is applied.
BKPT_TAG should be timed to the bus cycles since it is not latched. If extended past
the assertion of FREEZE, the negation of BKPT_TAG appears to the CPU32 as the
first DSCLK.
DSCLK is the gated serial clock. Normally high, it pulses low for each bit to be trans-
ferred. At the end of the seventeenth clock period, it remains high until the start of the
next transmission. Clock frequency is implementation dependent and may range from
DC to the maximum specified frequency. Although performance considerations might
dictate a hardware implementation, software solutions are not precluded, provided se-
rial bus timing is maintained.

7.2.8 Command Set

Following is a description of the command set available in BDM.
7.2.8.1 Command Format
The following standard bit format is utilized by all BDM commands.
15
OPERATION
Operation Field:
Commands are distinguished by the operation field. This 6-bit field provides for a
maximum of 64 unique commands.
R/W Field:
Direction of operand transfer is specified by this field. When the bit is set, the trans-
fer is from CPU to development system. When the bit is clear, data is written to the
CPU or to memory from the development system.
CPU32
REFERENCE MANUAL
BKPT_TAG
SHIFT_CLK
S1
RESET S2
FORCE_BGND R
Figure 7-9 BKPT/DSCLK Logic Diagram
10 9
0
EXTENSION WORD(S)
DEVELOPMENT SUPPORT
Q
Q
8 7 6 5
R/W OP SIZE 0
BKPT/DSCLK
4 3 2
0 A/D REGISTER
MOTOROLA
0
7-11