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DIVU
DIVUL
Instruction Format (long form):
15
14
13
0
1
0
0
REGISTER Dq
Instruction Fields:
Effective Address field — Specifies the source operand. Only data addressing modes
are allowed as shown:
Addressing Mode
Dn
An
(An)
(An) +
– (An)
(d
, An)
16
(d
, An, Xn)
8
(bd, An, Xn)
Register Dq field — Specifies a data register for the destination operand. The low-
order 32 bits of the dividend come from this register, and the 32-bit quotient is
loaded into this register.
Size field — Selects a 32 or 64 bit division operation.
0 — 32-bit dividend is in Register Dq.
1 — 64-bit dividend is in Dr:Dq.
Register Dr field — After the division, this register contains the 32-bit remainder. If Dr
and Dq are the same register, only the quotient is returned. If Size is 1, this
field also specifies the data register that contains the high-order 32 bits of the
dividend.
Overflow occurs if the quotient is larger than a 32-bit signed integer.
CPU32
REFERENCE MANUAL
Unsigned Divide
12
11
10
9
0
1
1
0
1
SIZE
0
Mode
Register
000
Reg. number: Dn
—
—
010
Reg. number: An
011
Reg. number: An
100
Reg. number: An
101
Reg. number: An
110
Reg. number: An
110
Reg. number: An
INSTRUCTION SET
8
7
6
5
0
0
1
0
0
0
0
Addressing Mode
(xxx).W
(xxx).L
#〈data〉
(d
, PC)
16
(d
, PC, Xn)
8
(bd, PC, Xn)
NOTE
DIVU
DIVUL
4
3
2
1
EFFECTIVE ADDRESS
MODE
REGISTER
0
0
REGISTER Dr
Mode
Register
111
000
111
001
111
100
111
010
111
011
111
011
MOTOROLA
0
4-71
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