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3.4.3.3 Program Counter Indirect with Index (Base Displacement)
This mode is similar to the address register indirect with index (base displacement)
mode described in 3.4.2.6 Address Register Indirect With Index (Base Displace-
ment), but the program counter is used as the base register. It requires an index reg-
ister indicator and an optional 16- or 32-bit sign-extended base displacement.
The operand is in memory. The address of the operand is the sum of the contents of
the program counter, the scaled contents of the sign-extended index register, and the
base displacement. The value of the program counter is the address of the first exten-
sion word. The reference is a program space reference and is only allowed for read
accesses.
In this mode, the program counter, the index register, and the displacement are all op-
tional. However, the user must supply the assembler notation "ZPC" (zero value is tak-
en for the program counter) to indicate that the program counter is not used. This
scheme allows the user to access the program space without using the program
counter in calculating the EA. The user can access the program space with a data reg-
ister indirect access by placing ZPC in the instruction and specifying a data register
(Dn) as the index register.
GENERATION:
ASSEMBLER SYNTAX:
MODE:
REGISTER:
PROGRAM COUNTER:
BASE DISPLACEMENT:
INDEX REGISTER:
SCALE:
MEMORY ADDRESS:
NUMBER OF EXTENSION WORDS:
3.4.3.4 Absolute Short Address
In this addressing mode, the operand is in memory, and the address of the operand is
in the extension word. The 16-bit address is sign extended to 32 bits before it is used.
GENERATION:
ASSEMBLER SYNTAX:
MODE:
REGISTER:
EXTENSION WORD:
MEMORY ADDRESS:
NUMBER OF EXTENSION WORDS:
MOTOROLA
DATA ORGANIZATION AND ADDRESSING CAPABILITIES
3-8
EA = (PC) + (Xn) + bd
(bd, PC, Xn. SIZE*SCALE)
111
011
31
SIGN-EXTENDED VALUE
31
SIGN-EXTENDED VALUE
1, 2, OR 3
EA GIVEN
(xxx).W
111
000
1
31
ADDRESS OF EXTENSION WORD
0
0
SCALE VALUE
X
31
OPERAND
31
15
SIGN EXTENDED
31
OPERAND
0
+
+
0
0
MEMORY ADDRESS
0
CPU32
REFERENCE MANUAL
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