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8.3.9 Shift/Rotate Instructions
The shift/rotate instruction table indicates the number of clock periods needed for the
processor to perform the specified operation on the given addressing mode. Footnotes
indicate when to account for the appropriate effective address times. The number of
bits shifted does not affect the execution time, unless noted. The total number of clock
cycles is outside the parentheses. The numbers inside parentheses (r/p/w) are includ-
ed in the total clock cycle number. All timing data assumes two-clock reads and writes.
LSd
LSd
LSd
ASd
ASd
ASd
ROd
ROd
ROd
ROXd
ROXd
ROXd
NOTES:
1. Head and cycle times can be calculated as follows:
Max (3 + (n/4) + mod(n,4) + mod (((n/4) + mod (n,4) + 1,2), 6)
or derived from the following table.
2. Head and cycle times are calculated as follows: (count ≤ 63): max (3 + n+ mod (n + 1,2), 6).
3. Head and cycle times are calculated as follows: (count ≤ 8): max (2 + n+ mod (n,2), 6).
d = Direction (left or right)
Clocks
6
0
8
7
10
15
12
23
14
31
16
39
18
47
20
55
22
63
CPU32
REFERENCE MANUAL
Instruction
Dn, Dm
#, Dm
〈FEA〉
Dn, Dm
#, Dm
〈FEA〉
Dn, Dm
#, Dm
〈FEA〉
Dn, Dm
#, Dm
〈FEA〉
1
2
3
10
11
13
18
19
21
26
27
29
34
35
37
42
43
45
50
51
53
58
59
61
INSTRUCTION EXECUTION TIMING
Head
Tail
−2
4
0
−2
4
0
−2
4
0
−2
−2
0
Shift Counts
4
5
6
14
16
17
22
24
25
30
32
33
38
40
41
46
48
49
54
56
57
62
Cycles
Note
0
(0/1/0)
1
0
6(0/1/0)
—
2
6(0/1/1)
—
0
(0/1/0)
1
0
6(0/1/0)
—
2
6(0/1/1)
—
0
(0/1/0)
1
0
6(0/1/0)
—
2
6(0/1/1)
—
0
(0/1/0)
2
0
(0/1/0)
3
2
6(0/1/1)
—
8
9
12
20
28
36
44
52
60
MOTOROLA
8-19
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