Functional Model Of Instruction Pipeline - Motorola CPU32 Reference Manual

Figure 7-11 Functional Model of Instruction Pipeline
Assertion of IPIPE for a single clock cycle indicates the use of data from IRB. Regard-
less of the presence of valid data in IRA, the contents of IRB are invalidated when
IPIPE is asserted. If IRA contains valid data, the data is copied into IRB (IRA → IRB),
and the IRB stage is revalidated.
Assertion of IPIPE for two clock cycles indicates the start of a new instruction and sub-
sequent replacement of data in IRC. This action causes a full advance of the pipeline
(IRB → IRC and IRA → IRB). IRA is refilled during the next instruction fetch bus cycle.
Data loaded into IRA propagates automatically through subsequent empty pipeline
stages. Signals that show the progress of instructions through IRB and IRC are nec-
essary to accurately monitor pipeline operation. These signals are provided by IRA
and IRB validity bits. When a pipeline advance occurs, the validity bit of the stage be-
ing loaded is set and the validity bit of the stage supplying the data is negated.
Because instruction execution is not timed to bus activity, IPIPE is synchronized with
the system clock and not the bus. Figure 7-12 illustrates the timing in relation to the
system clock.
IRA
CLKOUT
IPIPE
EXTENSION
WORD USED
Figure 7-12 Instruction Pipeline Timing Diagram
IPIPE should be sampled on the falling edge of the clock.
The assertion of IPIPE for a single cycle after one or more cycles of negation indicates
use of the data in IRB (advance of IRA into IRB). Assertion for two clock cycles indi-
cates that a new instruction has started (both IRA → IRB and IRB → IRC transfers
MOTOROLA
7-26
DATA
IRA
BUS
IRA
IRA IRB
INSTRUCTION
START
DEVELOPMENT SUPPORT
IRB IRC
EXTENSION OPCODES
WORDS RESIDUAL
IRA
IRC IRA IRA
EXTENSION
WORD USED
IRA IRA
IRB IRC
INSTRUCTION
START
CPU32
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